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IP1000A LF
Preliminary Data Sheet
Gigabit Ethernet NIC Single Chip
Features
PCI & DMA Features - PCI Specification Revision 2.3 compliant - 32-bit, 33/66MHz bus master capability - Efficient DMA operation maximizes PCI band-width utilization - 1 Terabyte (40 bit) address space - Scatter, gather transmit/receive DMA - Transmit "interrupt-less" mode of operation - Receive frame priority interrupts - Receive interrupt coalescing FIFO Features - No external memory required - Receive FIFO flow control thresholds - Configurable TX/RX FIFO MAC Features - IEEE 802.3z, 802.3x compliant - IEEE 802.1p, 802.1Q compliant - 1000Mbps, 100Mbps, 10Mbps triple speed, half/full duplex operation - Transmit and receive back to back frames at full wire speed - Half duplex carrier extension and packet bursting - Asymmetric/symmetric flow control - VLAN tag insertion/removal - VLAN tagged frame filtering - IPV4/6, TCP, UDP checksum calculation/ verification - 802.3 MIB statistic register sets - 64-bit hash table for multicast frame filtering - Jumbo frame support for transmit/receive - Big-endian Phsical Layer Features - Fully integrated IEEE 802.3ab compliant 1000BASE-T, 100BASE-TX and 10BASE-T port - DSP receiver includes feed-forward equalizer, decision feedback equalizer, echo canceller, crosstalk canceller, and baseline wander correction - 802.3ab compliant Auto-Negotiation for automatic speed, duplex, and master/slave configuration - Automatic MDI/MDI-X crossover function and polarity correction
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- - - - -
Automatic pair skew adjustment PHY management registers Smart Cable Analyzer (SCATM) Smart speed downshift APS(Auto Power Saving) a. Power Saving with Link status detecting b. Keep only MAC alive through software setting
Power Management, EEPROM and Package - WakeOnLAN support - ACPI Revision 1.0 compliant - 1.8/3.3V CMOS with 5V tolerant I/O - EEPROM 93C46 support - Optional boot from serial ROM support - 128-pin LQFP with e-PAD package Support Lead Free package (Please refer to the Order Information)
General Description
The IP1000A LF is a truly 10/100/1000Mbps Gigabit Ethernet NIC single chip which it incorporates a 32-bit PCI interface with bus master support. It is manufactured using standard digital CMOS process and contains all the active circuitry required to implement the physical layer functions to transmit and receive data on standard CAT5 unshielded twisted pair cable. The IP1000A LF is designed for use in a variety of applications including workstation NICs, and other systems utilizing a PCI bus. The IP1000A LF includes a 32-bit PCI bus interface, IEEE 802.3 compliant MAC, transmit and receive FIFO buffers, IEEE 802.3 compliant 10BASE-T, and 100BASE-TX PHY, IEEE 802.3z compliant 1000 BASE-T PHY, serial EEPROM interface, expansion ROM interface and LED drivers. The IP1000A LF supports features for use in "Green PCs" or systems where control over system power consumption is desired. The IP1000A LF supports several power down states, and the ability to issue a system "wake event" via reception of unique, user defined Ethernet frames. In addition, the IP1000A LF can assert a wake event in response to changes in the Ethernet link status.
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IP1000A LF
Preliminary Data Sheet
Block Diagram
PCI VDET INTAN RSTN PMEN PAR FRAMEN TRDYN IRDYN STOPN DEVSELN IDSEL PCICLK PERRN SERRN REQN GNTN CBEN[3:0] AD[31:0] ANALOG MISC CTRL_REGD CTRL_REGA RSET MAIN CLOCK X1 X2 POWER AND GROUND AVCCH AVCC AVSS VCC2 VCC1 VSS2 VSS1 MDI TP_MDI[3:0]+ TP_MDI[3:0]EEPROM EECS EESK EEDI EEDO Physical Media Access Control IP/TCP/UDP Checksum Verification RX FIFO Receive Flow Control (MAC) Layer (PCS, PMA, PMD) EXPANSION ROM BECS EESK EEDI EEDO BootRom_HOLD BootRom_WEN LED LED_LINK10N LED_LINK100N LED_LINK1000N LED_DUPLEXN LED_RXN LED_TXN
TX DMA Dual Queue Controller PCI Bus
TX FIFO
IP/TCP/UDP Checksum Generation Transmit Flow Control
Interface RX DMA Dual Queue Controller
32 bit Bus Master
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IP1000A LF
Preliminary Data Sheet
Table Of Contents
Features..................................................................................................................................................................................1 General Description...............................................................................................................................................................1 Block Diagram .......................................................................................................................................................................2 Table Of Contents..................................................................................................................................................................3 Revision History.....................................................................................................................................................................4 PIN Diagram ..........................................................................................................................................................................5 1 PIN Description .............................................................................................................................................................6 PIN Description (continued) .................................................................................................................................................7 PIN Description (continued) .................................................................................................................................................8 PIN Description (continued) .................................................................................................................................................9 2 Function Description...................................................................................................................................................10 2.1 Physical Layer...................................................................................................................... 10 2.1.1 Introduction ............................................................................................................. 10 2.1.2 Receiver Fucntion ................................................................................................... 10 2.1.3 Transmit Function ....................................................................................................11 2.1.4 Link Function............................................................................................................11 2.1.5 Smart Cable Analyzer (SCATM)............................................................................... 12 2.1.6 Smart Speed Downshift .......................................................................................... 12 2.2 PCI ....................................................................................................................................... 12 2.2.1 Reset ...................................................................................................13 2.2.2 FIFOs ...................................................................................................13 2.2.3 DMA ...................................................................................................13 2.2.4 Interrupts ................................................................................................................. 14 2.2.5 ACPI ...................................................................................................15 2.2.6 Wake On LAN ......................................................................................................... 16 2.3 Media Access Control .......................................................................................................... 19 2.3.1 VLAN ...................................................................................................20 2.3.2 Layer 3/4 Checksums ............................................................................................. 20 2.3.3 Flow Control............................................................................................................ 21 3 Register Description ...................................................................................................................................................22 3.1 PHY Registers...................................................................................................................... 22 3.1.1 Control Register (Reg0) .......................................................................................... 23 3.1.2 Status Register (Reg1)............................................................................................ 24 3.1.3 PHY Identifier Register (Reg2) ............................................................................... 25 3.1.4 PHY Identifier Register (Reg3) ............................................................................... 25 3.1.5 Advertisement Register (Reg4) .............................................................................. 25 3.1.6 Link Partner Ability Register (Base Page) (Reg5) .................................................. 26 3.1.7 Auto-Negotiation Expansion Register (Reg6)......................................................... 26 3.1.8 Auto-Negotiation Next Page Transmit Register (Reg7).......................................... 27 3.1.9 Auto-Negotiation Link Partner Next Page Register (Reg8) .................................... 27 3.1.10 1000BASE-T Control Register (Reg9).................................................................... 28 3.1.11 1000BASE-T Status Register (Reg10) ................................................................... 28 3.1.12 Extended Status Register (Reg15) ......................................................................... 29 3.2 MAC Registers..................................................................................................................... 30 3.2.1 Ethernet MIB Statistics............................................................................................ 30 3.2.2 PCI Configuration Space Registers ........................................................................ 47 3.2.3 EEPROM Fields...................................................................................................... 61 4 Absolute Maximum Ratings.......................................................................................................................................66 5 Operating Ranges.......................................................................................................................................................66 6 DC Characteristics......................................................................................................................................................66 7 Switching Characteristics...........................................................................................................................................68 8 Order Information........................................................................................................................................................74 9 Package Detail ............................................................................................................................................................75
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IP1000A LF
Preliminary Data Sheet
Revision History
Revision # IP1000A LF-DS-R01 IP1000A LF-DS-R02 IP1000A LF-DS-R03 Change Description 1. Initial release. 1. Adding package information, 128-pin LQFP with e-PAD, in page-1 and page-67 order information. 1. Modify I/O Register in page-4 and page-49 2. Modify Wake Signal in page-17, page-20 and page-60 3. Modify DeviceId in page-54 4. Modify Default setting as 0 in page-64 1. Add EXP-ROM Disable Bit in EEPROM content, in page64 2. Add EEPROM Disable Bit in EEPROM content, in page64 3. Add POA Disable Bit in EEPROM content, in page65 4. Add LED Mode, flashing speed and DSP setting parameter in EEPROM content, in page68 1. Add DC characteristic, in page69 2. Add EXP-ROM Timing diagram, in page71,72, 74, 75 3. Pin48 modify as "Left Floating", in page 7 4. RevisionID = 41, in page62 5. Delete POA description, in page1, 65 6. Modify jumbo description, in page1 7. Swap Pin31, Pin32 type Input and output, in page 8 1. Add detailed power consumption for for different voltage, in page 68 2. Remove IntRequested and countdown description, in page 15. 3. Remove receive interrupt coalescing description, in page 16. 4. Remove TCP segmenation, in page 23. 5. Modify VendorID description, in page62 6. Modify Minimum Core Voltage from 1.71V to 1.73V, in page68, 69 1. Add the order information for lead free package. 1. Remove description about 93C56, support 93C46 only, in page-1, 6
IP1000A LF-DS-R04
IP1000A LF-DS-R05
IP1000A LF-DS-R06
IP1000A LF-DS-R07 IP1000A LF-DS-R08
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PIN Diagram
DEVSELN STOPN PERRN VCC1 SERRN PAR VSS2 VSS1 VCC2 CBE1N AD15 AD14 AD13 AD12 AD11 AD10 VSS1 VCC1 VCC2 VSS2 AD9 AD8 CBE0N AD7 AD6 VSS1
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
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VCC1 AD5 AD4 AD3 VSS2 AD2 AD1 CTRL_REGD AD0 VCC1 VCC2 VSS1 VSS2 LED_LINK1000N(EE_OP) VCC1 LED_TXN LED_LINK10N (EESK) LED_LINK100N (EEDI) VSS1 VCC2 LED_RXN LED_DUPLEXN (EEDO) VSS2
IP1000A LF
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VCC1 TEST VCC2 BECS EECS VCC2 NC X2 X1 VSS2 RSET AVSS TP_MDI0 + TP_MDI0 AVSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
10 2 10 1 10 0 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
TRDYN IRDYN FRAMEN VCC2 VCC1 VSS2 CBE2N AD16 VSS1 AD17 VCC1 VCC2 AD18 VSS2 AD19 VSS1 AD20 AD21 AD22 AD23 IDSEL VCC1 CBE3N AD24 VSS1 AD25 AD26 VSS2 VCC2 AD27 AD28 AD29 AD30 AD31 REQN PCICLK VCC2 VSS2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
VSS1 PMEN GNTN RSTN VDET INTAN AVCC AVSS TP_MDI3 TP_MDI3 + AVSS AVCC AVSS TP_MDI2 TP_MDI2 + AVSS HSDAC_ P AVCCH AVSS CTRL_REGA AVCC AVSS TP_MDI1 TP_MDI1 + AVSS AVCC
IP1000A LF
Preliminary Data Sheet
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IP1000A LF
Preliminary Data Sheet
1
PIN Description
Type I/O Description Twisted- Pair Media Dependent Interface [3:0] In 1000BASE-T mode, all 4 pairs are both input and output at the same time. In 100BASE-TX and 10BASE-T mode, one pair of TP_MDI [1:0]+/- is used for transmit pair and the other is used for receive pair. TP_MDI [3:2]+/- are unused in 100BASE-TX and 10BASE-T mode. Test Pin Left floating Digital Regulator Control. Regulator control to generate 1.8V supply. Analog Regulator Control. Regulator control to generate 1.8V supply. Reference. External 6.2 kresistor connection as bandgap resistor. LINK 10Mb/s LED. 10BASE-T Link Indicator. This pin is shared with EEPROM/serial ROM clock LINK 100Mb/s LED. 100Mb/s Link Indicator. This pin is shared with EEPROM/serial ROM Data Input LINK 1000Mb/s LED. Duplex LED. Duplex or Duplex/Collision indicator. This pin is shared with the output from EEPROM/serial ROM Receive LED. Receive Activity. shared pin of output to serial Rom for HOLD Transmit LED. Transmit Activity. shared pin of output to serial Rom for write enable(active low)
Pin no. Label Medium Interface 36, 37, 41, TP_MDI [3:0]+/42, 50, 51, 55, 56
Analog misc 48 HSDAC_P 8 45 34 LED 17 CTRL_REGD CTRL_REGA RSET
O O O I
LED_LINK10N EESK LED_LINK100N EEDI LED_LINK1000N LED_DUPLEXN EEDO LED_RXN BootRom_HOLD LED_TXN BootRom_WEN
O O O O O LI O I O
18
14 22
21
16
O
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IP1000A LF
Preliminary Data Sheet
PIN Description (continued)
Pin no. Main Clock 31 32 X2 X1 Label Type O I Description Reference Clock. 25 MHz crystal reference. Reference Clock. 25 MHz crystal reference or oscillator input. Power Detect. The IP1000A LF detects whether PCI bus power supply is available or not from this pin. Interrupt Request, asserted LOW. The IP1000A LF asserts INTAN to request an interrupt, when any one of the programmed interrupt event occurs. Reset, asserted LOW. RSTN will cause the IP1000A LF to reset all of its functional blocks. RSTN must be asserted for a minimum duration of 10 PCICLK cycles. While RSTN is asserted, the IP1000A LF PCI interface is placed in an isolated state. When the IP1000A LF PCI bus is isolated, all PCI output and bi-directional signals are placed in a high impedance state, and all inputs are ignored. The IP1000A LF will remain in a reset state for approximately 380ns following the de-assertion of RSTN. Wake Event, assertion level is programmable. The IP1000A LF asserts PMEN to signal the detection of a wake event. The PMEN signal eventually drives the PCI bus PME# signal, but not intended to be directly connected to PME#. See the PCI Bus Power Management Interface Specification for details on generating PME# from PMEN. Parity. PCI Bus parity is even across bits 0 through 31 of AD and bits 0 through 3 of CBEN. The IP1000A LF generates PAR during address and write data phases as a bus master, and during read data phase as a target. It checks for correct parity during read data phase as bus master, during every address phase as a bus slave, and during write data phases as a target. PCI Bus Cycle Frame, asserted LOW. FRAMEN is asserted at the beginning of the address phase of the bus transaction and de-asserted before the final transfer of the data phase of the transaction. Target Ready, asserted LOW. A bus target asserts TRDYN to indicate valid read data phases, and to indicate it is ready to accept data during write data phases. A bus master will monitor TRDYN.
PCI interface 60 VDET
I
59
INTAN
O
61
RSTN
I
63
PMEN
O
108
PAR
I/O
100
FRAMEN
I/O
102
TRDYN
I/O
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IP1000A LF
Preliminary Data Sheet
PIN Description (continued)
Pin no. Label PCI interface (continued) 101 IRDYN Type I/O Description Initiator Ready, asserted LOW. A bus master asserts IRDYN to indicate valid data phases on AD during write data phases, and to indicate it is ready to accept data during read data phases. A target will monitor IRDYN. Stop, asserted LOW. STOPN is driven by the slave target to inform the bus master to terminate the current transaction. Device Select, asserted LOW. The IP1000A LF asserts DEVSELN when it is selected as a target during a bus transaction. It monitors DEVSELN for any target to acknowledge a bus transaction initiated by the IP1000A LF. Initialization Device Select. The IDSEL is used to select the IP1000A LF during configuration read and write transactions. PCI Bus Clock. This clock is used to drive the PCI bus interfaces and the internal DMA logic. All bus signals are sampled on the rising edge of PCICLK. PCICLK can operate from 0MHz to 66MHz, on a PCI bus. Parity Error, asserted LOW. The IP1000A LF asserts PERRN when it checks and detects a bus parity error. When it is generating PAR output, the IP1000A LF monitors for any reported parity error on PERRN. System Error, asserted LOW. Request, asserted LOW. The IP1000A LF asserts REQN to request PCI bus master operation. PCI Bus Grant, asserted LOW. GNTN signals access to the PCI bus has been granted to IP1000A LF. PCI Bus Command/Byte Enable, asserted LOW. Bus command and byte enables are multiplexed on the CBEN signals. CBEN specify the bus command during the address phase transaction, and carry byte enables during the data phase.
104
STOPN
I/O
103
DEVSELN
I/O
82
IDSEL
I
67
PCICLK
I
105
PERRN
I/O
107 68
SERRN REQN
O O
62
GNTN
I
80, 96, 112, 125
CBE [3:0] N
I/O
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IP1000A LF
Preliminary Data Sheet
PIN Description (continued)
Pin no. Label Type I/O Description PCI Bus Address/Data. Address and data are multiplexed on the AD pins. Bits 0 through 31 carry the lower 32 bits of the physical address during the first clock cycle of a transaction, and carry data during the subsequent clock cycles. PCI address/data bus 2, 3, 4, 6, 7, 9, AD [31:0] 69, 70, 71, 72, 73, 76, 77, 79, 83, 84, 85, 86, 88, 90, 93. 95, 113, 114, 115, 116, 117, 118, 123, 124, 126, 127,
EEPROM interface / EXPANSION ROM BECS 27 O 28 Test pins 25 30 EECS TEST NC O I,PU I,PU
Boot ROM Chip Select Note: EESK, EEDI, EEDO are shared with EEPROM EEPROM Chip Select Selection of internal test ( tied to ground for normal mode ) NC
Analog Power and Ground 47 AVCCH 39, 44, 53, 58 AVCC 35, 38, 40, 43, 46, 49, 52, 54, 57 AVSS
Power Analog Power 3.3V Power Analog Power 1.8V. Ground Analog Ground
Digital Power and Ground 11, 20, 26, 29, VCC2 66, 74, 91, 99, 111, 121 1, 10, 15, 24, VCC1 81, 92, 98, 106, 120 5, 13, 23, 33, VSS2 65, 75, 89, 97, 109, 122 8, 12, 19, 64, VSS1 78, 87, 94, 110, 119, 128
Power Digital I/O Power 3.3V
Power Digital Core Power 1.8V.
Ground Digital Ground
Ground Digital Ground
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IP1000A LF
Preliminary Data Sheet
2
2.1
2.1.1
Function Description
Physical Layer
Introduction Figure 2-1 : DSP Function Block Diagram
Waveshape Filter 10/100/1000 Transmit PCS Balance FIFO Echo Canceller NEXT Canceller De-skew FIFO Gain Control Baseline Wander Compensation
TX_EN TX_ER TXD[7:0] GTX_CLK TX_CLK COL
DAC
DRIVER
TP_MDI[3:0] FFE ADC Hybrid
RX_DV RX_ER RXD[7:0] RX_CLK CRS 10/100/ 1000 Receive PCS
DFE/VITERBI
Timing Recovery
10BASE-T Receiver
DPLL MDC MDIO INT# Serial Interface Management PHY Registers Auto-Negotiation
With state-of-the-art DSP mixed-mode technology, the physical layer of IP1000A LF is designed to accomplish low power, high performance, and full integration for 1000BASE-T, 100BASE-TX, and 10BASE-T operation. The IP1000A LF eastablish a proper link mode with its link partner through Auto-Negotiation process. Automatic MDI/MDI-X crossover function and wire polarity correction capability ensure robust data exchange over CAT5 UTP cables. Channel skews among different pairs of the cable are also automatically adjusted. 2.1.2 2.1.2.1 Receiver Fucntion Active Hybrid
The IP1000A LF implements an on-chip hybrid to reduce the near-end echo by subtracting the replica of the transmitted signal from the input signal. This hybrid relieves the precision requirement of ADC and the digital echo canceller. 2.1.2.2 Analog to Digital Converter (ADC)
The ADC function block converts analog signal to digitized samples at 125MHz. With an advanced architecture and high linearity, the ADC is able to provide excellent quantization accuracy for subsequent digital signal processing.
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IP1000A LF
Preliminary Data Sheet
Echo Canceller
2.1.2.3
With the proprietary architecture, the adaptive digital echo canceller further reduces the residual echo not removed by the hybrid, the reflection due to patch cord impedance mismatch and non-ideal cable characteristics. 2.1.2.4 NEXT Canceller
When IP1000A LF is operated in 1000BASE-T mode, it uses 4 pairs of wires to transmit and receive data at the same time. This results in a detrimental near-end crosstalk between adjacent pairs and significantly impairs the receiver performance. An adaptive digital NEXT canceller is implemented in IP1000A LF to mitigate this effect. 2.1.2.5 Baseline Wander Canceller
IP1000A LF implements a digital adaptive baseline wander cancellation circuit to compensate DC shifts, which are result of the DC loss from the transformer. 2.1.2.6 Feed-Forward Equalizer (FFE) and Decision-Feedback Equalizer (DFE)
The FFE and DFE of IP1000A LF are designed to remove inter-symbol interference. These fully adaptive filters can track the inherently time-variant channel environment. 2.1.2.7 Digital Timing Recovery
IP1000A LF adopts a digital timing recovery scheme to accurately acquire the timing information at the receiver side. This advanced digital timing recovery block reduces both long-term and short-term frequency jitter to achieve as low bit error rate as possible. The maximum frequency offset it can track far exceeds the requirement of the IEEE standard. 2.1.2.8 Decoder
The IP1000A LF implements different decoders for 1000BASE-T, 100BASE-TX, and 10BASE-T respectively. 2.1.3 2.1.3.1 Transmit Function Digital to Analog Converter (DAC)
The IP1000A LF incorporates a hightly integrated DAC to transmit Normal Link Pulse (NLP), Fast Link Pulse (FLP), Manchester coded symbols, MLT3 waveform, or partial response PAM5 signals. 2.1.3.2 Encoder
The IP1000A LF implements different encoders for 1000BASE-T, 100BASE-TX, and 10BASE-T respectively. 2.1.4 2.1.4.1 Link Function Medium Dependent Interface (MDI)
The IP1000A LF transmits and receives data with all four pairs of wires in 1000BASE-T mode. If the IP1000A LF is operated in 100BASE-TX or 10BASE-T mode, only one pair is responsible for transmitting and the other for receiving data. 2.1.4.2 Automatic MDI/MDI-X Crossover and Pair Polarity Correction
The IP1000A LF is able to correct pair polarity errors in all modes. The automatic crossover function will adjust MDI/MDI-X crossover condition for proper operation. In addition, the IP1000A LF can also correct two types of abnormal cable configuration not compliant with the IEEE 802.3ab standard. This function can be turned off by setting PHY register 20.2 to "0".
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IP1000A LF
Preliminary Data Sheet
Table Assignment of PMA signal to MDI and MDI-X pin-outs
RJ-45 Contact 1 2 3 6 4 5 7 8 2.1.4.3
IP1000A LF pins TP_MDI[0]+ TP_MDI[0]TP_MDI[1]+ TP_MDI[1]TP_MDI[2]+ TP_MDI[2]TP_MDI[3]+ TP_MDI[3]-
MDI BI_DA+ BI_DA BI_DB+ BI_DB BI_DC + BI_DC BI_DD+ BI_DD -
MDI-X BI_DB+ BI_DB BI_DA+ BI_DA BI_DD+ BI_DD BI_DC+ BI_DC -
Abnormal type 1 Abnormal type 2 BI_DA+ BI_DA BI_DB+ BI_DB BI_DD+ BI_DD BI_DC+ BI_DC BI_DB+ BI_DB BI_DA+ BI_DA BI_DC + BI_DC BI_DD+ BI_DD -
Auto-Negotiation and Next Page Exchange
When the IP1000A LF is not set in forced mode, Auto-Negotiation automatically configures IP1000A LF for 1000BASE-T/100BASE-TX/10BASE-T, full/half duplex, and master/slave operation based on the highest common factor of both link capabality. IP1000A LF is able to perform next page exchanges. This function can be turned on/off manually by changing the register setting (PHY register 4.15). The content of the next page is based on PHY registers 7 and 8, respectively. When IP1000A LF is operated in 1000BASE-T, the next page exchanges are automatically turned on. 2.1.5 Smart Cable Analyzer (SCATM)
To simplify the Gigabit link establishment, the IP1000A LF incorporates the "Smart Cable Analyzer" (SCATM) feature . This feature helps to make cable diagnosis an easy task for end users. If there is an improperly installed cable, the signal quality can be severly deteriorated to prevent from achieving a high SNR, which as result this leads to a poor networking performance. Furthermore, if the cable is open-circuited or short-circuited in any pair of wires, a Gigabit link is impossible. SCA can detect opens, shorts or impedance mismatch of a cable. It can also pinpoint the distance of the problematic segment to enable a quick troubleshooting. 2.1.6 Smart Speed Downshift
A normal CAT5 cable has four pairs of wires. However, there exist some legacy cables with only two pairs of wires sufficient for a successful 100Mbps or 10Mbps operation. With the such cables, two Gigabit devices can agree on 1000Mbps speed via Auto-Negotiation but will never set up a successful link. The IP1000A LF can detect this "hangup" condition and downshifts to 100Mbps speed after several repeated failed tries in 1000 Mbps mode. The default downshift feature is turned on. It can be turned off by setting PHY register 16.11 to "0".
2.2
PCI
The PCI Bus Interface (PBI) implements the procedures and algorithms needed to link the IP1000A LF to a PCI bus. The IP1000A LF can be either a PCI bus master or slave. The PBI is also responsible for managing the DMA interfaces and the host processor accessing to the IP1000A LF registers. The PBI also manages interrupt generation for a host processor.
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IP1000A LF
Preliminary Data Sheet
The IP1000A LF supports all of the PCI memory commands and decides on a burst-by-burst basis to issue which command to use in order to maximize bus efficiency. The list of PCI memory commands used by the IP1000A LF is shown below. For all commands, read and write commands are with respect to the IP1000A LF (i.e. read implies the IP1000A LF obtains information from an off-chip location, write implies the IP1000A LF sends information to an offchip location). Memory Read (MR) Memory Read Line (MRL) Memory Read Multiple (MRM) Memory Write (MW) Memory Write Invalidate (MWI) MR is used for all fetches of descriptor information. For reads of transmit frame data, MR, MRL, or MRM is used, depending upon the remaining number of bytes in the fragment, the amount of free space in the Transmit FIFO, and whether the Receive DMA Logic is requesting a bus master operation. MW is used for all descriptor writes. Writes of receive frame data use either MW or MWI, depending upon the remaining number of bytes in the fragment, the amount of frame data in the Receive FIFO, and whether the Transmit DMA Logic is requesting a bus master operation. The IP1000A LF provides two configuration bits to control the use of advanced memory commands. The MwlEnable bit in the ConfigCommand register allows the host to enable or disable the use of MWI. The MWIDisable bit in the DMACtrl register allows the host system the ability to disable the use of MWI PCI command. The IP1000A LF provides a set of registers that control the PCI burst behavior. These registers allow a trade-off to be made between PCI bus efficiency and underrun/overrun frequency. In support of bus isolation requirements for system states in which the IP1000A LF is powered down, all IP1000A LF PCI outputs will enter the tri-state condition when the RSTN is active. 2.2.1 Reset
When the host system issues a reset to the IP1000A LF via the AsicCtrl register, a delay of at least 5ms is required before any register access should be attempted. 2.2.2 FIFOs
The IP1000A LF uses a single configurable 32KB single-port SRAM for both the transmit and receive FIFOs. 2.2.3 DMA
The IP1000A LF implements scatter gather Direct Memory Access (DMA) for moving data from the IP1000A LF to/from the host's system memory. Two independent DMA processes are used to transfer transmit data from host system memory to the IP1000A LF (transmit DMA), and to transfer receive data from the IP1000A LF to host system memory (receive DMA). 2.2.3.1 Transmit DMA
To utilize the IP1000A LF to transmit data onto a Gigabit Ethernet network, the data to be transmitted must be transferred from the host's system memory to the IP1000A LF. The data bus utilized by the IP1000A LF for this data transfer is the PCI bus, and the method for transferring the data is DMA. The locations within system memory which contain the data to be transmitted are indicated to the IP1000A LF using Transmit Frame Descriptors.
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IP1000A LF
Preliminary Data Sheet
The Transmit Frame Descriptor (TFD) is a data structure containing fields specifying a pointer to another TFD (the TFDNextPtr field), control information (the TFC0 field), and from one to 15 pointers to locations within system memory containing the Ethernet frame data (the FragInfo fields). The TFD is used to indicate to the IP1000A LF which blocks of system memory comprise the Ethernet frame data to be transmitted. Each Ethernet frame is described by one and only one TFD. 2.2.3.2 Receive DMA
To utilize the IP1000A LF to receive data from a Gigabit Ethernet network, the received data must be transferred from the IP1000A LF to the host's system memory. The data bus utilized by IP1000A LF for this data transfer is the PCI bus, and the method for transferring the data is DMA. The locations within system memory reserved for the received data are indicated to IP1000A LF using Receive Frame Descriptors. The Receive Frame Descriptor (RFD) is a data structure containing fields specifying a pointer to another RFD (the RFDNextPtr field), status information (the RFS field), and one pointer (the FragInfo field) to a unique, contiguous block of system memory which is reserved for holding the received data. Typically, one RFD will completely specify a single received Ethernet frame. While it is possible to use multiple RFDs to describe a single Ethernet frame, it is not possible to describe multiple Ethernet frames with a single RFD. 2.2.4 Interrupts
The IP1000A LF generates host system processor interrupts via the PCI bus based on events related to transmit and receive DMA operation. It is the responsibility of the host system to detect these interrupts, identify the corresponding condition which caused the interrupt, and take the appropriate action. At gigabit per second data rates, interrupts related to Gigabit Ethernet frame transmission and reception can quickly overwhelm a host system processor. The IP1000A LF incorporates several features for minimizing the number of interrupts generated. These features should be carefully understood and utilized to achieve maximum system performance in Gigabit Ethernet networks. 2.2.4.1 Transmit DMA Interrupts
Interrupts can be generated by the IP1000A LF based on a number of events related to transmit DMA operation: TxDMAComplete interrupt is issued after successful transfer of an Ethernet frame to the IP1000A LF via transmit DMA with the TxDMAIndicate bit in the TFD's TFC0 field is a logic 1. Use of this interrupt is not recommended due to the frequency of transmit DMA operations in a Gigabit Ethernet network. TxComplete interrupt (frame transmission complete without error) is issued after successful transmission of an Ethernet frame which has already been transferred to the IP1000A LF with the TxIndicate bit in the TFD's TFC0 field is a logic 1. A recommended use of this feature is to avoid setting the TxIndicate bit in every TFD, but instead only set the TxIndicate bit in the last TFD of a TFDList, or in every Nth frame (where N>1). TxComplete interrupt (frame transmission encountered an error) is issued if an error occurs during transmission of an Ethernet frame which has already been transferred to the IP1000A LF independent of the TxIndicate bit setting in the TFD's TFC0 field. When an error occurs, the transmit MAC of the IP1000A LF is disabled (and must be re-enabled to resume operation). Transmit DMA operation continues in spite of transmit errors except for the case of a transmit underrun error (indicated by the TxUnderrun bit in the TxStatus register). To resume transmit DMA operation after a transmit underrun error, the transmit DMA, transmit FIFO, and transmit MAC functions within IP1000A LF must be reset.
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A common use of interrupts during transmit DMA operation is to determine which TFDs have been successfully transmitted so the host system can free the memory occupied by old TFDs. Interrupts however usually incur a significant cost in terms of host system performance, requiring a large percentage of processor time to service. While interrupts are expensive, memory is usually abundant, therefore a trade off which minimizes interrupts in exchange for more memory usage is desirable. 2.2.4.2 Interrupt-Less Transmit DMA
IP1000A LF's transmit DMA can operate without generating host system processor interrupts. In this mode of operation, the host system does not set the TxIndicate or TxDMAIndicate bits in the TFC0 field of any TFDs used to transfer Ethernet frames from system memory. Thus, an interrupt is not issued by the IP1000A LF to indicate successful DMA transfer or successful transmission of each Ethernet frame. An interrupt will only be issued by the IP1000A LF in the event of a transmit error, but this case should be rare. Without the use of interrupts, the IP1000A LF provides another mechanism for the host system to determine which Ethernet frames have been successfully transmitted. This mechanism allows the host system to free memory locations holding old TFD lists. This "interrupt-less" mechanism involves using the TxFrameId field of the TxStatus register. The TxFrameId field of the TxStatus register indicates the last Ethernet frame which was successfully transmitted. Using this information, the host system can infer successful transmission of all Ethernet frames up to the frame indicated by the TxFrameId field of the TxStatus register. Thus, the host system decides when to poll the TxFrameId field of the TxStatus register (for example, when the amount of memory occupied by old TFD lists becomes excessive) and avoid generation of processor intensive interrupts by the IP1000A LF. 2.2.4.3 Receive DMA Interrupts
Interrupts can be generated by the IP1000A LF based on a number of events related to receive DMA operation: RxDMAComplete interrupt is issued after successful transfer of one or more Ethernet frames (based on the interrupt coalescing configuration) from the IP1000A LF to the host system memory. Interrupt coalescing should be used in conjunction with the RxDMAComplete interrupt given the frequency of frame receipts in a Gigabit Ethernet network. RxDMAPriority interrupt is issued if a received Ethernet frame contains a Tag Control Information field with priority greater than or equal to the priority set in the RxDMAIntCtrl register. RFDListEnd interrupt is issued if the end of the RFD list is reached (indicated by an RFDNextPtr field with a value of 0x0000000000), or a RFD with the RFDDone bit of the RFS field with a value of logic 1 is encountered. 2.2.4.4 Receive DMA Interrupt Coalescing
A common use of interrupts during receive DMA operation is to indicate when new Ethernet frames have been transferred to host system memory. Interrupts however usually incur a significant cost in terms of host system performance, requiring a large percentage of processor time to service. One way to minimize the number of interrupts issued by the IP1000A LF related to receive DMA operation is to issue a single interrupt to indicate multiple Ethernet frames have been received. While minimizing interrupts can improve host system performance, it can also require more host system memory usage, and increase network latency. Therefore, a balance between interrupt frequency and network latency must be reached by the host system to optimize performance. Note: interrupt coalescing only applies to the nominal TFD list. Priority TFD lists do not utilize interrupt coalescing. 2.2.5 ACPI
The IP1000A LF supports operating system directed power management according to the ACPI specification. Power management registers in the PCI configuration space, as defined by the PCI Bus Power Management Interface specification, Revision 1.1
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IP1000A LF
Preliminary Data Sheet
Power Management States
2.2.5.1
The IP1000A LF supports several power management states. The PowerState field in the PowerMgmtCtrl register determines IP1000A LF's current power state. The power states are defined as follows: D0 Uninitialized (power state 0) is entered as a result of hardware reset, or after a transition from D3 Hot to D0. This state is the same as D0 Active except that the PCI configuration registers are uninitialized. In this state, the IP1000A LF responds to PCI configuration cycles only. D0 Active (power state 0) is the normal operational power state for the IP1000A LF. In this state, the PCI configuration registers have been initialized by the system, including the IoSpace, MemorySpace, and BusMaster bits in the ConfigCommand register, so the IP1000A LF is able to respond to PCI I/O, memory and configuration cycles and can operate as a PCI master. The IP1000A LF cannot signal wake (PMEN on the PCI bus) from the D0 state. D1 (power state 1) is a "light-sleep" state. The IP1000A LF optionally supports this state determined by the D1Support bit in the ConfigParm word in the EEPROM. The D1 state allows transition back to D0 with no delay. In this state, the IP1000A LF responds to PCI configuration accesses, to allow the system to change the power state. The IP1000A LF's function in the D1 state is to recognize wake events and link state events and pass them on to the system by asserting the PMEN signal on the PCI bus. D2 (power state 2) is a partial power-down state. The IP1000A LF optionally supports this state determined by the D2Support bit in the ConfigParm word in the EEPROM. D2 allows a faster transition back to D0 than is possible from the D3 state. In this state, the IP1000A LF responds to PCI configuration accesses, to allow the system to change the power state. In D2 the IP1000A LF does not respond to any PCI I/O or memory accesses. The IP1000A LF's function in the D2 state is to recognize wake events and link state events and pass them on to the system by asserting the PMEN signal on the PCI bus. D3 Hot (power state 3) is the full power-down state for the IP1000A LF. In this state, the IP1000A LF responds to PCI configuration accesses, to allow the system to change the power state back to D0 Uninitialized. In D3 hot, the IP1000A LF does not respond to any PCI I/O or memory accesses. The IP1000A LF's main responsibility in the D3 Hot state is to recognize wake events and link state events and signal those to the system by asserting the PMEN signal on the PCI bus. D3 Cold (power state undefined) is the power-off state for the IP1000A LF. The IP1000A LF does not function in this state. When power is restored, the system guarantees the assertion of hardware reset, which puts the IP1000A LF into the D0 Uninitialized state. 2.2.6 Wake On LAN
Wake on LAN is a key component of the IBM/Intel(R) Advanced Manageability Alliance (AMA) initiative. The IP1000A LF implements a portion of the Wake On LAN functionality defined by the AMA initiative. Specifically, the IP1000A LF can be configured to respond to wake up frames sent by a Wake On LAN managerment station. 2.2.6.1 Wake Events
The IP1000A LF can generate wake events to the system as a result of Wake Packet reception, Magic Packet reception, or due to a change in the link status. The WakeEvent register gives the host system control over which of these events are passed to the system. Wake events are signaled over the PCI bus using the PMEN signal. A Wake Packet event is controlled by the WakePktEnable bit in WakeEvent register. The WakePktEnable bit has no effect when IP1000A LF is in the D0 power state, as the wake process can only take place in states D1, D2, or D3. When the IP1000A LF detects a Wake Packet, it signals a wake event on PMEN (if PMEN assertion is enabled), and sets the WakePktEvent bit in the WakeEvent register. The IP1000A LF can signal that a wake event has occurred when it receives a pre-defined frame from another station. The host system transfers a set of frame data patterns into the transmit FIFO using the TxDMA function before placing the IP1000A LF in a power-down state. Once powered down, the IP1000A LF compares
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IP1000A LF
Preliminary Data Sheet
receive frames with the frame patterns in the transmit FIFO. When a matching frame is received (and also passes the filtering mode set in the Receive-Mode register), a wake event is signaled. Frame patterns are written to the transmit FIFO in a single "pseudo-packet". Prior to transferring this pseudo-packet, the host system should first set the TxReset in the AsicCtrl (to reset the transmit FIFO pointers and prevent transmission) then prepare a TFD that points to a single data buffer. The buffer should contain one or more frame patterns placed contiguously. The number of frame patterns is limited by the transmit FIFO size. The FragLen field in the TFD must exactly equal the sum of the frame pattern bytes. Also, the host system must set the WordAlign field to `x1' in the TFC0 field of the TFD to prevent frame word-alignment. Finally, the host system must write the TFD's address to the TFDListPtr register to transfer the frame into the transmit FIFO. The frame patterns in the transmit FIFO specify which bytes in received frames are to be examined. Each byte in the transmit FIFO specifies a four bit relative offset (from the start of the received frame) in the most significant nibble and a four bit length indicator in the least significant nibble. Relative offsets describe the number of bytes of the received frame to skip from the last relevant byte, beginning with byte 0x00. Relative offsets with a value of 0xF indicate the actual relative offset is larger than 15, and is specified by the next 8 bit value in the transmit FIFO. Length indicators with a value of 0xF indicate the actual length indicator is larger than 15, and is specified by the next 8 bit value in the transmit FIFO. If both the relative offset, and the length indicator are 0xF, the first byte following the relative offset/length indicator pair is the actual relative offset, and the second following byte is the actual length indicator. A byte value of 0x00 indicates the end of the pattern for that wake frame. Immediately following the end-of-pattern is a 4-byte CRC. The calculation used to for the CRC is the same polynomial as the Ethernet MAC FCS. An example pseudo-packet (based on the ARP packet example from Appendix A of the "OnNow Network Device Class Power Management Specification") which would be loaded into the transmit FIFO of the IP1000A LF is shown in Figure 2-2. Figure 2-2 : Example Pseudo Packet
TxFIFO 0xc2 0x71 0xf4 0x10 pseudo packet 0x00 0xf3 0x19
offset and length indicator pairs
end of pattern
CRC to match
0x08 0xd7
Table 2-1 deciphers the pseudo packet inFigure 2-2 indicating the relative offset and length indicators which the IP1000A LF will apply to all receive frames.
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Table 2-1 : Example Pseudo Packet Field Breakdown
PSEUDO PACKET OFFSET/ LENGTH INDICATOR PAIRS 0xC2 0x71 0xF4 0x10
ACTUAL RELATIVE OFFSET 0xC 0x7 0x10
ACTUAL LENGTH INDICATOR 0x2 0x1 0x4
If the pseudo packet shown in Figure 2-2 and described in Table 2-1 is placed into the IP1000A LF's transmit FIFO, for each received frame the IP1000A LF will take a CRC over the bytes described inTable 2-2. Table 2-2 : Relationship Between Pseudo Packet and Receive Frame Bytes ACTUAL RELATIVE OFFSET 0xC 0x7 0x10 ACTUAL LENGTH INDICATOR 0x2 0x1 0x4 BYTE OFFSETS OF RECEIVE FRAME TO CALCULATE CRC OVER 0xC, 0xD 0x15 0x26, 0x27, 0x28, 0x29
If a CRC calculation over the received frame bytes indicated by the pseudo packet (in this example, those bytes described byTable 2-2) matches the CRC value in the pseudo packet (in this example 0xF31908D7) the IP1000A LF will assert a wake event. Note, this matching technique may result in false wake events being reported to the host system as it is possible that more than one set of byte values specified by the pseudo packet may result in the same CRC value. The IP1000A LF also supports Magic PacketTM technology developed by Advanced Micro Devices to allow remote wake-up of a sleeping station on a network via transmission of a special frame. Once the IP1000A LF has been placed in Magic Packet mode and put to sleep, it scans all incoming frames addressed to it for a data sequence consisting of 16 consecutive repetitions of its own 48-bit Ethernet MAC StationAddress. This sequence can be located anywhere within the frame, but must be preceded by a synchronization stream. The synchronization stream is defined as 6 bytes of 0xFF. For example, if the MAC address programmed into the StationAddress register is 0x11:22:33:44:55:66, then the IP1000A LF would be scanning for the frame data shown in Figure 2-3.
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Figure 2-3 : Example Magic Packet
Received Packet
0xFFFFFFFFFFFF 0x112233445566 0x112233445566 0x112233445566 0x112233445566 0x112233445566 0x112233445566 0x112233445566 0x112233445566 0x112233445566 0x112233445566 0x112233445566 0x112233445566 0x112233445566 0x112233445566 0x112233445566 0x112233445566
Magic Packet wake up is controlled by the MagicPktEnable bit in the WakeEvent register. A wake event can only take place in the D1, D2, or D3 states, and the MagicPktEnable bit has no effect when the IP1000A LF is in the D0 power state. The Magic Packet must also pass the address matching criteria set in ReceiveMode register. A Magic Packet may also be a broadcast frame. When the IP1000A LF detects a Magic Packet, it signals a wake event on PMEN (if PMEN assertion is enabled), and sets the MagicPktEvent bit in the WakeEvent register. The IP1000A LF can also signal a wake event when it senses a change in the network link state, from "link up" to "link fail", or vice versa. Link state wake is controlled by the LinkEventEnable bit in the WakeEvent register. At the time LinkEventEnable bit is set by the host system, the IP1000A LF samples the current link state. It then waits for the link state to change. If the link state changes before the IP1000A LF returns to state D0 or the LinkEventEnable bit is cleared, the LinkEvent bit is set in the WakeEvent register, and (if it is enabled) the PMEN signal is asserted.
2.3
Media Access Control
The MAC block implements the IEEE Ethernet 802.3 Media Access Control functions with Full Duplex and Flow Control enhancements. In half duplex mode, the MAC implements the Carrier Sense Multiple Access with Collision Detect (CSMA/CD) protocol. Full duplex mode by definition does not utilize CSMA/CD, allowing data to be transmitted on demand. An optional flow control mechanism in full duplex mode is provided via the MAC Control PAUSE function. Additionally, the MAC also performs these functions in either half or full duplex mode: Optional transmit frame check sequence (FCS) generation Padding to the minimum legal frame size
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Preamble and SFD generation Preamble and SFD removal Receive frame FCS checking and optional FCS stripping Receive frame destination address matching Support for multicast and broadcast frame reception or rejection (via filtering) In addition, the MAC is responsible for generation of hardware signals to update the internal statistics counters. 2.3.1 VLAN
Virtual Local Area Network (VLAN) technology is used to regulate broadcast and multicast traffic in switched Ethernet networks. VLAN technology utilizes Ethernet frame tagging, providing Ethernet switches a mechanism to correlate a specific Ethernet frame with a specific group of end stations. Using this correlation, Ethernet switches in a network are able to regulate broadcast and multicast VLAN tagged frames, forwarding such frames only to those nodes which are members of the same VLAN (instead of to all nodes). In this way, broadcast and multicast network utilization is minimized. The IEEE defines VLANs as follows: VLANs facilitate easy administration of logical groups of stations that can communicate as if they were on the same LAN. They also facilitate easier administration of moves, adds and changes in members of these groups. Traffic between VLANs is restricted. Bridges forward unicast, multicast and broadcast traffic only on LAN segments that serve the VLAN to which the traffic belongs. As far as possible, VLANs maintain compatibility with existing bridges and end-stations. Detailed information on VLAN implementation is located in the following standards: IEEE 802.1Q Virtual Bridged Local Area Networks (also now part of ISO/IEC 15802-3: 1998). Specifies the operation of VLAN enabled Ethernet bridges, and defines the tagged frame format. IEEE 802.3ac Frame Extensions for Virtual Bridged Local Area Networks (VLAN) Tagging on 802.3 Networks. Modifies the IEEE 802.3 specification to accommodate tagging for VLANs as specified in IEEE 802.1Q. The IP1000A LF supports VLANs with the following functions: Transmission and reception of VLAN tagged frames, increasing the maximum frame size by four octets. VLAN tags for transmit frames may be applied either by the host system prior to transfer of the frame to the IP1000A LF via the transmit DMA process, or by the IP1000A LF via the VLAN tag information specified in the TFC0 or the VLANTag register. The the TFC0 VLANTagInsert field, and MACCtrl register AutoVLANtagging bit determines the source for VLAN frame tagging with the TFC0 VLANTagInsert having priority over the MACCtrl register AutoVLANtagging bit. Any VLAN tagged frames received by the IP1000A LF may be transferred to the host system unmodified, or stripped of all VLAN tags as determined by the MACCtrl register AutoVLANuntagging bit. For any received frame which contains a VLAN tag, regardless of the state of the MACCtrl register AutoVLANuntagging bit, the VLAN tag is copied to the RFS TCI field. The priority of VLAN tagged frames received by the IP1000A LF may be detected and based on the programmable PriorityThresh field of the RxDMAIntCtrl register, an interrupt asserted via the RxDMAPriority field of the IntStatus or IntStatusAck register. Using the ReceiveVLANMatch or ReceiveVLANHash fields of the ReceiveMode register, only VLAN tagged frames with specified VLAN ID values are passed to the host system. All other VLAN tagged frames and all un-tagged frames are dropped. 2.3.2 Layer 3/4 Checksums
The Ethernet Carrier Sense Multiple Access with Collision Detect (CSMA/CD) protocol comprises a portion of Layer 2 within the Open Systems Interconnect (OSI) Seven Layer Model of network systems. Ethernet incorporates a CRC capability (via the FCS field) in an attempt to check for errors during transmission.
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Higher layer protocols which utilize Ethernet may also utilize checksums in addition to the Ethernet FCS. These higher layer protocol checksums are typically calculated by the host system, and inserted within the Ethernet frame (for transmit data) prior to frame transfer to the IP1000A LF via the transmit DMA process. Similarly, higher layer protocol checksums within received Ethernet frames are verified by the host system after the frames have been transferred from the IP1000A LF via receive DMA process. The IP1000A LF can perform checksum calculations, and verifications for three popular higher layer protocols. Internet Protocol version 4 (Layer 3 within the OSI model) defined in RFC 791 Transmission Control Protocol (Layer 4 within the OSI model) defined in RFC 793 User Datagram Protocol (Layer 4 within the OSI model) defined in RFC 768 By configuring the IP1000A LF to perform the checksum calculations for the supported protocols, the host system working load is lightened resulting in higher performance. The IP1000A LF will check each frame for the respective checksum functions which are selected and will not calculate or insert IPv4/TCP/UDP checksums if the frame data does not contain an IPv4 datagram (or IPv6 datagram if the IPv6Enable bit is a logic 1), TCP segment, or UDP datagram. If the host system does not want the IP1000A LF to calculate and insert IPv4/TCP/UDP checksums, the respective checksum bits within the TFC0 field must be a logic 0. 2.3.3 Flow Control
The IP1000A LF supports both asymmetric and symmetric IEEE 802.3 flow control via the MAC Control PAUSE function. Any IEEE 802.3 flow control compliant node receiving a PAUSE control frame must inhibit frame transmission for the amount of time specified in the PAUSE control frame. The pause time is specified in pause quanta (in Gigabit Ethernet, a pause quanta is 512 bit times and a bit time is 1ns). The maximum pause time is 65,535 pause quanta, or 33.6ms. Asymmetric operation corresponds to the IP1000A LF acting on PAUSE frames received from a Gigabit Ethernet network. Symmetric operation corresponds to the IP1000A LF both acting on received PAUSE frames, and transmitting PAUSE frames onto a Gigabit Ethernet network. Use of asymmetric and symmetric flow control is Typically determined during auto negotiation. When participating in symmetric flow control operation, transmit PAUSE control frames can be generated by the host system, or automatically by the IP1000A LF. The host system may use any mechanism to determine when to transfer a PAUSE control frame to the IP1000A LF. Automatic generation of PAUSE control frames by the IP1000A LF is related to the state of the receive FIFO. If the receive FIFO fills beyond a host system configurable point (the flow control on threshold, as defined by the FlowOnThresh register), the IP1000A LF will automatically transmit a PAUSE control frame in an attempt to halt the transmitting node. The flow control on threshold, above which the IP1000A LF sends a PAUSE control frame, must be chosen carefully to account for receive frames already in transit. A general rule is to set the flow control on threshold offset (the difference between the maximum size of the FIFO and the flow control on threshold) equal to or greater than twice the size (in bytes) of the maximum expected receive frame size. Once the receive FIFO fills to the point defined by the FlowOnThresh register, a PAUSE frames is transmitted for each non-MAC control frame received by the IP1000A LF, until the receive FIFO empties to the point defined by the FlowOffThresh register.
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3
Register Description
Table 3-1 : Abbreviation Description Abbreviation SC LH LL R R/W Description Self-Clear Latched High Latched Low Read Only Read and Write
3.1
PHY Registers
The IP1000A LF includes a full set of PHY registers which can be accessed through the internal MDC/MDIO interface. Table 3-2 : PHY Register Map Register Reg0 Reg1 Reg2 Reg3 Reg4 Reg5 Reg6 Reg7 Reg8 Reg9 Reg10 Reg11 Reg12 Reg13 Reg14 Reg15 Reg16 Reg17 Reg18 Reg19 Description Control Register Status Register PHY Identifier Register PHY Identifier Register Auto-Negotiation advertise register Link Partner Ability Register Auto-Negotiation Expansion Register Auto-Negotiation Next Page Transmit Register Auto-Negotiation Link Partner Next Page Register 1000BASE-T Control Register 1000BASE-T Status Register Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
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Control Register (Reg0)
3.1.1
Class............................. PHY Registers Access Method ............. Indirect access via PhyCtrl(Offset 0x76) registers Register Address .......... 0x0 Default .......................... 0x1140 Width ............................ 16 bits Bit 0.5:0 0.6 BIT Name Reserved Speed Selection (MSB) 0.6 0.13 1 1 = Reserved 1 0 = 1000Mb/s 0 1 = 100Mb/s 0 0 = 10Mb/s 1 = Enable COL signal test 0 = Disable COL signal test 1 = Full duplex 0 = Half duplex 1 = Restart Auto-Negotiation Process 0 = Normal operation 1 = electrically Isolate PHY from MII or GMII 0 = normal operation 1 = Power down 0 = Normal operation 1 = Enable Auto-Negotiation Process 0 = Disable Auto-Negotiation Process 0.6 0.13 1 1 = Reserved 1 0 = 1000Mb/s 0 1 = 100Mb/s 0 0 = 10Mb/s 1 = enable loopback mode 0 = disable loopback mode 1 = PHY software reset 0 = normal operation BIT Description Type RO R/W HW SW Reset Reset Always 0 1 Update
0.7 0.8 0.9 0.10 0.11 0.12 0.13
Collision Teset Duplex Mode Restart Auto-NEG Isolate Power Down Auto-Negotiation Enable Speed Selection (LSB)
R/W R/W R/W SC R/W R/W R/W R/W
0 1 0 0 0 1 0
0 Update SC 0 0 Update Update
0.14 0.15
Loopback Software Reset
R/W R/W SC
0 0
0 0 (SC)
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Status Register (Reg1)
3.1.2
Class............................. PHY Registers Access Method ............. Indirect access via PhyCtrl(Offset 0x76) registers Register Address .......... 0x1 Default .......................... 0x7949 Width ............................ 16 bits Bit 1.0 1.1 1.2 1.3 1.4 1.5 1.6 BIT Name Extended Capability Jabber Detect Link Status Auto-Negotiation Ability Remote Fault Auto-Negotiation Complete MF Preamble Suppression BIT Description 1 = extended register capabilities 0 = basic register set capabilities only 1 = jabber condition detected 0 = no jabber condition detected 1 = link is up 0 = link is down 1 = PHY is able to perform Auto-Negotiation 0 = PHY is not able to perform Auto-Negotiation 1 = remote fault condition detected 0 = no remote fault condition detected 1 = Auto-Negotiation process completed 0 = Auto-Negotiation process not completed 1 = PHY will accept management frames with preamble uppressed. 0 = PHY will not accept management frames with preamble uppressed. ignore when read 1 = Extended status information in Register 15 0 = No extended status information in Register 15 Type RO RO LH RO LL RO RO LH RO RO HW Reset 1 0 0 1 0 0 SW Reset 1 0 0 1 0 0
Reserved 1
1.7 1.8 1.9 1.10 1.11
Reserved Extended Status
RO RO RO RO RO
Reserved 0 Reserved 1 Reserved 0 Reserved 0 1 1
100BASE-T2 Half 1 = PHY able to perform half duplex 100BASE-T2 Duplex 0 = PHY not able to perform half duplex 100BASE-T2 100BASE-T2 Full 1 = PHY able to perform full duplex 100BASE-T2 0 = PHY not able to perform full duplex 100BASE-T2 Duplex 10Mb/s Half Duplex 1 = PHY able to operate at 10 Mb/s in half duplex mode 0 = PHY not able to operate at 10 Mb/s in half duplex mode 10 Mb/s Full Duplex 1 = PHY able to operate at 10Mb/s in full duplex mode 0 = PHY not able to operate at 10Mb/s in full duplex mode 100BASE-X Half Duplex 100BASE-X Full Duplex 100BASE-T4 1 = PHY able to perform half duplex 100BASE-X 0 = PHY not able to perform half duplex 100BASE-X 1 = PHY able to perform full duplex 100BASE-X 0 = PHY not able to perform full duplex 100BASE-X 1 = PHY able to perform 100BASE-T4 0 = PHY not able to perform 100BASE-T4
1.12
RO
1
1
1.13 1.14 1.15
RO RO RO
1 1
1 1
Reserved 0
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PHY Identifier Register (Reg2)
3.1.3
Class............................. PHY Registers Access Method ............. Indirect access via PhyCtrl(Offset 0x76) registers Register Address .......... 0x2 Default .......................... 0x0243 Width ............................ 16 bits Bit BIT Name BIT Description 0000001001000011 note : ICPLUS OUI is 0x0090C3 Type RO HW SW Reset Reset Always 0x243
2.15:0 Organizationally Unique Identifier Bit [3:18] 3.1.4
PHY Identifier Register (Reg3)
Class............................. PHY Registers Access Method ............. Indirect access via PhyCtrl(Offset 0x76) registers Register Address .......... 0x3 Default .......................... 0x0C80 Width ............................ 16 bits Bit 3.3:0 3.9:4 BIT Name Revision Number 0000 Manufacturer's Model Number 001000 note 3.a: This Model Number is for IP1000A LF, IP100 Model Number is 000100 000011 BIT Description Type RO RO HW Reset SW Reset
Always 0000 Always 001000
3.15:10 Organizationally Unique Identifier Bit [19:24] 3.1.5
RO
Always 000011
Advertisement Register (Reg4)
Class............................. PHY Registers Access Method ............. Indirect access via PhyCtrl(Offset 0x76) registers Register Address .......... 0x4 Default .......................... 0x01E1 Width ............................ 16 bits Bit 4.4:0 4.5 4.6 4.7 4.8 BIT Name Selector Filed 10BASE-T Half Duplex 10BASE-T Full Duplex 100BASE-TX Half Duplex 00001 = 802.3 1 = Advertise 0 = Not advertised 1 = Advertise 0 = Not advertised 1 = Advertise 0 = Not advertised BIT Description Type RO R/W R/W R/W R/W HW Reset 00001 1 1 1 1 SW Reset 00001 1 1 1 1
100BASE-TX Full 1 = Advertise Duplex 0 = Not advertised
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IP1000A LF
Preliminary Data Sheet
BIT Name 100BASE-T4 PAUSE Asymmetric Pause Reserved Remote Fault Reserved Next Page BIT Description 1 = Capable of 100BASE-T4 0 = Not capable of 100BASE-T4 1 = MAC PAUSE implemented 0 = MAC PAUSE not implemented 1 = Asymmetric Pause 0 = No asymmetric Pause ignore when read 1 = Set Remote Fault bit 0 = Do not set Remote Fault bit ignore when read 1 = Advertise 0 = Not advertised Type RO R/W R/W R/W R/W RO R/W HW Reset SW Reset
Bit 4.9 4.10 4.11 4.12 4.13 4.14 4.15
Reserved 0 0 0 0 0 0
Reserved 0 0
3.1.6
Link Partner Ability Register (Base Page) (Reg5)
Class............................. PHY Registers Access Method ............. Indirect access via PhyCtrl(Offset 0x76) registers Register Address .......... 0x5 Default .......................... 0x0 Width ............................ 16 bits Bit 5.4:0 BIT Name Selector Field BIT Description Received Code Work Bit 4:0 Received Code Work Bit 12:5 Received Code Work Bit 13 Received Code Work Bit 14 Received Code Work Bit 15 Type RO RO RO RO RO HW Reset 0 0 0 0 0 SW Reset 0 0 0 0 0
5.12:5 Technology Ability Field 5.13 5.14 5.15 3.1.7 Remote Fault Acknowledge Next Page
Auto-Negotiation Expansion Register (Reg6)
Class............................. PHY Registers Access Method ............. Indirect access via PhyCtrl(Offset 0x76) registers Register Address .......... 0x6 Default .......................... 0x0004 Width ............................ 16 bits Bit 6.0 BIT Name Link Partner Auto-Negotiation Able Page Received BIT Description 1 = Link Partner is Auto-Negotiation able 0 = Link Partner is not Auto-Negotiation able 1 = A New Page has been received 0 = A New Page has not been received Type RO HW Reset 0 SW Reset 0
6.1
RO LH
0
0
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IP1000A LF
Preliminary Data Sheet
BIT Name Local Next Page Able BIT Description 1 = Local Device is Next Page able 0 = Local Device is not Next Page able Type RO RO RO HW Reset 0 0 0 SW Reset 0 0 0
Bit 6.2 6.3 6.4
Link Partner Next 1 = Link Partner is Next Page able Page Able 0 = Link Partner is not Next Page able
Parallel Detection 1 = A fault has been detected via the Parallel Fault Detection function 0 = A fault has not been detected via the Parallel Detection function 6.15:5 Reserved Ignore when read 3.1.8 Auto-Negotiation Next Page Transmit Register (Reg7)
RO
Reserve 0
Class............................. PHY Registers Access Method ............. Indirect access via PhyCtrl(Offset 0x76) registers Register Address .......... 0x7 Default .......................... 0x2001 Width ............................ 16 bits Bit BIT Name BIT Description Type R/W RO R/W R/W RO R/W HW Reset 0x001 0 0 1 0 SW Reset 0x001 0 0 1 0
7.10:0 Message/ Transmit Code Word Bit 10:0 Unformatted Field 7.11 7.12 7.13 7.14 7.15 3.1.9 Toggle Acknowledge 2 Message Page Reserved Next Page Transmit Code Word Bit 11 Transmit Code Word Bit 12 Transmit Code Word Bit 13 Transmit Code Word Bit 14 Transmit Code Word Bit 15
Reserved 0
Auto-Negotiation Link Partner Next Page Register (Reg8)
Class............................. PHY Registers Access Method ............. Indirect access via PhyCtrl(Offset 0x76) registers Register Address .......... 0x8 Default .......................... 0x0 Width ............................ 16 bits Bit 8.10 8.11 8.12 8.13 8.14 8.15 BIT Name BIT Description Type RO RO RO RO RO RO HW Reset 0x000 0 0 0 0 0 SW Reset 0x000 0 0 0 0 0
Message/ Received Code Word Bit 15 Unformatted Field Toggle Received Code Word Bit 15 Acknowledge 2 Message Page Acknowledge Next Page Received Code Word Bit 15 Received Code Word Bit 15 Received Code Word Bit 15 Received Code Word Bit 15
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IP1000A LF
Preliminary Data Sheet
1000BASE-T Control Register (Reg9)
3.1.10
Class............................. PHY Registers Access Method ............. Indirect access via PhyCtrl(Offset 0x76) registers Register Address .......... 0x9 Default .......................... 0x0 Width ............................ 16 bits Bit 9.7:0 9.8 9.9 9.10 9.11 9.12 BIT Name Reserved BIT Description Ignore when read Type R/W R/W R/W R/W R/W R/W HW SW Reset Reset Reserved to 0x00 0 0 0 0 0 0 0 0 0 0
1000BASE-T Half 1 = Advertise 0 = Not advertise Duplex 1000BASE-T Full 1 = Advertise Duplex 0 = Not advertise Port Type Configuration Value Manual Configuration Enable 1 = Prefer multi-port device (MASTER) 0 = Prefer single-port device (SLAVE) 1 = Manual configure as MASTER 0 = Manual configure as SLAVE 1 = Manual Configuration Enable 0 = Automatic Configuration
9.15:13 Test mode
000 = Normal Mode R/W 001 = Test Mode 1 - Transmit waveform Test 010 = Test Mode 2 - Transmit Jitter Test (MASTER mode) 011 = Test Mode 3 - Transmit Jitter Test (SLAVE mode) 100 = Test Mode 4 - Transmit Distortion Test 101, 110, 111 = Reserved
000
000
3.1.11
1000BASE-T Status Register (Reg10)
Class............................. PHY Registers Access Method ............. Indirect access via PhyCtrl(Offset 0x76) registers Register Address .......... 0xA Default .......................... 0x0 Width ............................ 16 bits Bit BIT Name BIT Description Type RO RO RO RO HW Reset SW Reset
10.7:0 Idle Error Count 10.8 Reserved 10.9 10.10 Reserved
Ignore when read Ignore when read
0x00 0x00 Reserved to 0 Reserved to 0 0 0
Link Partner 1 = Link Partner is capable of 1000BASE-T half 1000BASE-T Half duplex Duplex Capability 0 = Link Partner is not capable of 1000BASE-T half duplex
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IP1000A LF
Preliminary Data Sheet
BIT Name BIT Description Type RO HW Reset 0 SW Reset 0
Bit 10.11
10.12 10.13 10.14
Link Partner 1 = Link Partner is capable of 1000BASE-T full 1000BASE-T Full duplex Duplex Capability 0 = Link Partner is not capable of 1000BASE-T full duplex Remote Receiver 1 = Remote Receiver OK Status 0 = Remote Receiver Not OK Local Receiver Status MASTER/SLAVE Configuration Resolution 1 = Local Receiver OK 0 = Local Receiver Not OK 1 = Local PHY configuration resolved to MASTER 0 = Local PHY configuration resolved to SLAVE
RO RO RO
0 0 0
0 0 0
10.15
MASTER/SLAVE 1 = MASTER/SLAVE configuration fault detected Configuration 0 = No MASTER/SLAVE configuration fault detected Fault
RO LH SC
0
0
3.1.12
Extended Status Register (Reg15)
Class............................. PHY Registers Access Method ............. Indirect access via PhyCtrl(Offset 0x76) registers Register Address .......... 0xF Default .......................... 0xC000 Width ............................ 16 bits Bit BIT Name BIT Description Ignore when read Type RO RO RO RO RO HW SW Reset Reset 0x000 0x000 1 1 0 0 1 1 0 0
15.11:0 Reserved 15.12 15.13 15.14 15.15
1000BASE-T Half 1 =PHY able to perform half duplex 1000BASE-T Duplex 0 =PHY not able to perform half duplex 1000BASE-T 1000BASE-T Full 1 =PHY able to perform full duplex 1000BASE-T Duplex 0 =PHY not able to perform full duplex 1000BASE-T 1000BASE-X Half Duplex 1000BASE-X Full Duplex 1 =PHY able to perform half duplex 1000BASE-X 0 =PHY not able to perform half duplex 1000BASE-X 1 =PHY able to perform full duplex 1000BASE-X 0 =PHY not able to perform full duplex 1000BASE-X
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IP1000A LF
Preliminary Data Sheet
3.2
3.2.1
MAC Registers
Ethernet MIB Statistics
The host interacts with the IP1000A LF mainly through slave registers, which occupy 256 bytes in the host system's I/O space, 512 bytes in memory space, or both. Generally, registers are referred to as "I/O registers", implying that the registers may in fact be mapped and accessed by the host system in memory space. These registers must be accessed with instructions that are no larger than the bit-width of the register being accessed. There are several classes of I/O registers, with Ethernet Management Information Base (MIB) Statistics comprising a portion of the total I/O register space. The Ethernet MIB Statistic registers implement several counters defined in the IEEE 802.3 standard. Table 3-3 : IP1000A LF Ethernet MIB Statistics Register Map CLK Tx Tx Tx Tx Tx Tx Tx Tx Tx Tx Tx Tx Rx Rx Rx Rx Rx Rx Rx Rx Rx Rx BcstFramesRcvdOk McstFramesRcvdOk FramesRcvdOk BcstOctetRcvOk McstOctetRcvdOk OctetRcvOk FramesLostRxErrors InRangeLengthErrors MacControlFramesRcvd BYTE 4 BYTE 3 BYTE 2 BYTE 1 ADDR OFFSET FC F8 F4 SingleColFrames MultiColFrames LateCollisions FramesWDeferredXmt McstFramesXmtdOk FramesXmtdOk BcstOctetXmtOk McstOctetXmtOk OctetXmtOk FramesCheckSeqErrors FrameTooLongErrors F0 EC E8 E4 E0 DC D8 D4 D0 CC C8 C4 C0 BC B8 B4 B0 AC A8
FramesWEXDeferal MacControlFramesXmtd BcstFramesXmtdOk
FramesAbortXSColls CarrierSenseErrors
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IP1000A LF
Preliminary Data Sheet
3.2.1.1
BcstFramesRcvdOk
Class............................. Ethernet MIB Statistics I/O Base Address ......... IoBaseAddress register value Memory Base Address . MemBaseAddress register value Address Offset .............. 0xBC Default Value ................ 0x0000 Access Rule.................. Word Width ............................ 16 bits Bit 15..0 BIT Name BIT Description Type R/W HW Reset SW Reset
BcstFramesRcvd Broadcast Frames Received OK is the count of Ok the number of frames that are successfully received with destination address equal to the broadcast address (0xFFFFFFFFFFFF). Bcst-FramesRcvdOk does not include frames received with frames too long, FCS, length or alignment errors, or frames lost due to internal MAC sublayer error (i.e. overrun). BcstFramesRcvdOk will wrap around to zero after reaching 0xFFFF. See IEEE 802.3 Clause 30.3.1.1.22. An UpdateStats interrupt (UpdateStats bit within the IntStatus register) will occur when BcstFramesRcvdOk reaches a value of 0xC000. BcstFramesRcvdOk is enabled by writing a logic 1 to the StatisticsEnable bit in the MACCtrl register, and a logic 0 to the BcstFramesRcvdOk bit within the StatisticsMask register.
3.2.1.2
BcstFramesXmtdOk
Class............................. Ethernet MIB Statistics I/O Base Address ......... IoBaseAddress register value Memory Base Address . MemBaseAddress register value Address Offset .............. 0xF6 Default Value ................ 0x0000 Access Rule.................. Word Width ............................ 16 bits Bit 15..0 BIT Name BIT Description Type HW Reset SW Reset
BcstFramesXmtd Broadcast Frames Transmitted is the count of the R/W Ok number of frames that are successfully transmitted to the broadcast address (0xFFFFFFFFFFFF). Frames transmitted to other multicast addresses are excluded from this statistic. Bcst-FramesXmtdOk will wrap around to zero after reaching 0xFFFF. See IEEE 802.3 Clause 30.3.1.1.19. An UpdateStats interrupt (UpdateStats bit within the IntStatus register) will occur when
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IP1000A LF
Preliminary Data Sheet
BIT Name BIT Description BcstFramesXmtdOk reaches a value of 0xC000. BcstFramesXmtdOk is enabled by writing a logic 1 to the StatisticsEnable bit in the MACCtrl register, and a logic 0 to the BcstFramesXmtdOk bit within the StatisticsMask register. Type HW Reset SW Reset
Bit
3.2.1.3
BcstOctetRcvOk
Class............................. Ethernet MIB Statistics I/O Base Address ......... IoBaseAddress register value Memory Base Address . MemBaseAddress register value Address Offset .............. 0xB0 Default Value ................ 0x00000000 Access Rule.................. Double Word Width ............................ 32 bits Bit 31..0 BIT Name BcstOctetRcvOk BIT Description Type HW Reset SW Reset
Broadcast Octets Received OK is the count of the R/W number of data and padding octets in frames, with destination address equal to the broadcast address (0xFFFFFFFFFFFF), that are successfully received. BcstOctetRcvOk does not include frames received with frames too long, FCS, length or alignment errors, or frames lost due to internal MAC sublayer error (i.e. overrun). BcstOctetRcvOk will wrap around to zero after reaching 0xFFFFFFFF. All IP1000A LF byte and octet count based statistic registers include the VLAN tag (4 octets) regardless of whether or not the IP1000A LF is adding (on frame transmission) or removing (on frame reception) the VLAN tag automatically. An UpdateStats interrupt (UpdateStats bit within the IntStatus register) will occur when BcstOctetRcvOk reaches a value of 0xC0000000. BcstOctetRcvOk is enabled by writing a logic 1 to the StatisticsEnable bit in the MACCtrl register, and a logic 0 to the BcstOctetRcvOk bit within the StatisticsMask register.
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IP1000A LF
Preliminary Data Sheet
3.2.1.4
BcstOctetXmtOk
Class............................. Ethernet MIB Statistics I/O Base Address ......... IoBaseAddress register value Memory Base Address . MemBaseAddress register value Address Offset .............. 0xD8 Default Value ................ 0x00000000 Access Rule.................. Double Word Width ............................ 32 bits Bit 31..0 BIT Name BcstOctetXmtOk BIT Description Type HW Reset SW Reset
Broadcast Octets Transmitted OK is a count of R/W data and padding octets of frames successfully transmitted to a the broadcast address (0xFFFFFFFFFFFF). BcstOctetXmtOk will wrap around to zero after reaching 0xFFFFFFFF. All IP1000A LF byte and octet count based statistic registers include the VLAN tag (4 octets) regardless of whether or not the IP1000A LF is adding (on frame transmission) or removing (on frame reception) the VLAN tag automatically. An UpdateStats interrupt (UpdateStats bit within the IntStatus register) will occur when BcstOctetXmtOk reaches a value of 0xC0000000. BcstOctetXmtOk is enabled by writing a logic 1 to the StatisticsEnable bit in the MACCtrl register, and a logic 0 to the BcstOctetXmtOk bit within the StatisticsMask register.
3.2.1.5
CarrierSenseErrors
Class............................. Ethernet MIB Statistics I/O Base Address ......... IoBaseAddress register value Memory Base Address . MemBaseAddress register value Address Offset .............. 0xF8 Default Value ................ 0x0000 Access Rule.................. Word Width ............................ 16 bits Bit 15..0 BIT Name BIT Description Type HW Reset SW Reset
CarrierSenseErrors Carrier Sense Errors counts the number of times R/W that the carrier sense signal (CRS) was de-asserted (a logic 0) during the transmission of a frame without collision. The carrier sense signal is not monitored for the purpose of this statistic until after the preamble and start-of-frame delimiter fields of the Ethernet frame have been transmitted. CarrierSenseErrors will wrap around to zero after reaching 0xFFFF. See IEEE 802.3 Clause 30.3.1.1.13. An UpdateStats interrupt (UpdateStats bit within
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IP1000A LF
Preliminary Data Sheet
BIT Name BIT Description the IntStatus register) will occur when CarrierSenseErrors reaches a value of 0xC000. CarrierSenseErrors is enabled by writing a logic 1 to the StatisticsEnable bit in the MACCtrl register, and a logic 0 to the CarrierSenseErrors bit within the StatisticsMask register. Type HW Reset SW Reset
Bit
3.2.1.6
FramesAbortXSColls
Class............................. Ethernet MIB Statistics I/O Base Address ......... IoBaseAddress register value Memory Base Address . MemBaseAddress register value Address Offset .............. 0xFC Default Value ................ 0x0000 Access Rule.................. Word Width ............................ 16 bits Bit 15..0 BIT Name FramesAbortXSColls BIT Description Type HW Reset SW Reset
Frames Aborted Due to Excess Collisions counts R/W the number of frames which are not transmitted successfully due to excessive collisions. FramesAbortXSColls will wrap around to zero after reaching 0xFFFF. See IEEE 802.3 Clause 30.3.1.1.11. An UpdateStats interrupt (UpdateStats bit within the IntStatus register) will occur when FramesAbortXSColls reaches a value of 0xC000. FramesAbortXSColls is enabled by writing a logic 1 to the StatisticsEnable bit in the MACCtrl register, and a logic 0 to the FramesAbortXSColls bit within the StatisticsMask register.
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IP1000A LF
Preliminary Data Sheet
FramesCheckSeqErrors
3.2.1.7
Class............................. Ethernet MIB Statistics I/O Base Address ......... IoBaseAddress register value Memory Base Address . MemBaseAddress register value Address Offset .............. 0xCC Default Value ................ 0x0000 Access Rule.................. Word Width ............................ 16 bits Bit 15..0 BIT Name BIT Description Type HW Reset SW Reset
FramesCheckSeq Frame Check Sequence Errors is a count of R/W Errors received frames that are an integral number of octets in length and do not pass the FCS check. This does not include frames received with frame-too-long, or frame-too-short (runt) errors. FramesCheck-SeqErrors will wrap around to zero after reaching 0xFFFF. See IEEE 802.3 Clause 30.3.1.1.6. An UpdateStats interrupt (UpdateStats bit within the IntStatus register) will occur when FramesCheckSeqErrors reaches a value of 0xC000. FramesCheckSeqErrors is enabled by writing a logic 1 to the StatisticsEnable bit in the MACCtrl register, and a logic 0 to the FramesCheckSeqErrors bit within the StatisticsMask register.
3.2.1.8
FramesLostRxErrors
Class............................. Ethernet MIB Statistics I/O Base Address ......... IoBaseAddress register value Memory Base Address . MemBaseAddress register value Address Offset .............. 0xCE Default Value ................ 0x0000 Access Rule.................. Word Width ............................ 16 bits Bit 15..0 BIT Name FramesLostRxErrors BIT Description Type HW Reset SW Reset
Frames Lost Due to Receive Errors is a count of R/W the number of frames that should have been received (the destination address matched the filter criteria) but experienced a receive FIFO overrun error (the receive FIFO does not have enough free space to store the received data). FramesLostRxErrors only includes overruns that become apparent to the host system, and does not include frames that are completely ignored due to a completely full receive FIFO at the beginning of frame reception. FramesLostRxErrors will wrap around to zero
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Preliminary Data Sheet
BIT Name BIT Description after reaching 0xFFFF. See IEEE 802.3 Clause 30.3.1.1.15. An UpdateStats interrupt (UpdateStats bit within the IntStatus register) will occur when FramesLostRxErrors reaches a value of 0xC000. FramesLostRxErrors is enabled by writing a logic 1 to the StatisticsEnable bit in the MACCtrl register, and a logic 0 to the FramesLostRxErrors bit within the StatisticsMask register. Type HW Reset SW Reset
Bit
3.2.1.9
FramesRcvdOk
Class............................. Ethernet MIB Statistics I/O Base Address ......... IoBaseAddress register value Memory Base Address . MemBaseAddress register value Address Offset .............. 0xB4 Default Value ................ 0x00000000 Access Rule.................. Double Word Width ............................ 32 bits Bit 31..0 BIT Name FramesRcvdOk BIT Description Type HW Reset SW Reset
Frames Received OK is the count of the number R/W of frames that are successfully received. FramesRcvdOk does not include frames received with frames too long, FCS, length or alignment errors, or frames lost due to internal MAC sublayer error (i.e. overrun). FramesRcvdOk will wrap around to zero after reaching 0xFFFFFFFF. See IEEE 802.3 Clause 30.3.1.1.5. An UpdateStats interrupt (UpdateStats bit within the IntStatus register) will occur when FramesRcvdOk reaches a value of 0xC0000000. FramesRcvdOk is enabled by writing a logic 1 to the StatisticsEnable bit in the MACCtrl register, and a logic 0 to the FramesRcvdOk bit within the StatisticsMask register.
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Preliminary Data Sheet
3.2.1.10 FramesWDeferredXmt Class............................. Ethernet MIB Statistics I/O Base Address ......... IoBaseAddress register value Memory Base Address . MemBaseAddress register value Address Offset .............. 0xE4 Default Value ................ 0x00000000 Access Rule.................. Double Word Width ............................ 32 bits Bit 31..0 BIT Name BIT Description Type HW Reset SW Reset
FramesWDeferred Frames with Deferred Transmit is a count of the R/W Xmt number of frames that must delay their first attempt of transmission because the medium was busy. Frames involved in any collisions are not counted by FramesWDeferredXmt. FramesWDeferredXmt wrap around to zero after reaching 0xFFFFFFFF. See IEEE 802.3 Clause 30.3.1.1.9. An UpdateStats interrupt (UpdateStats bit within the IntStatus register) will occur when FramesWDeferredXmt reaches a value of 0xC0000000. FramesWDeferredXmt is enabled by writing a logic 1 to the StatisticsEnable bit in the MACCtrl register, and a logic 0 to the FramesWDeferredXmt bit within the StatisticsMask register.
3.2.1.11 FramesWEXDeferal Class............................. Ethernet MIB Statistics I/O Base Address ......... IoBaseAddress register value Memory Base Address . MemBaseAddress register value Address Offset .............. 0xFE Default Value ................ 0x0000 Access Rule.................. Word Width ............................ 16 bits Bit 15..0 BIT Name FramesWEXDeferal BIT Description Type HW Reset SW Reset
Frames with Excessive Deferals counts the R/W number of frames that deferred for an excessive period of time (exceeding the defer limit). FramesWEXDeferal is only incremented once per LLC frame. FramesWEXDeferal will wrap around to zero after reaching 0xFFFF. See IEEE 802.3 Clause 30.3.1.1.20. An UpdateStats interrupt (UpdateStats bit within the IntStatus register) will occur when FramesWEXDeferal reaches a value of 0xC000. FramesWEXDeferal is enabled by writing a logic 1 to the StatisticsEnable bit in the MACCtrl register, and a logic 0 to the FramesWEXDeferal bit within the StatisticsMask register.
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IP1000A LF
Preliminary Data Sheet
3.2.1.12 FramesXmtdOk Class............................. Ethernet MIB Statistics I/O Base Address ......... IoBaseAddress register value Memory Base Address . MemBaseAddress register value Address Offset .............. 0xDC Default Value ................ 0x00000000 Access Rule.................. Double Word Width ............................ 32 bits Bit 31..0 BIT Name FramesXmtdOk BIT Description Type HW Reset SW Reset
Frames Transmitted OK is a count of the number R/W of frames that are successfully transmitted. FramesXmtdOk will wrap around to zero after reaching 0xFFFFFFFF. See IEEE 802.3 Clause 30.3.1.1.2. An UpdateStats interrupt (UpdateStats bit within the IntStatus register) will occur when FramesXmtdOk reaches a value of 0xC0000000. FramesXmtdOk is enabled by writing a logic 1 to the StatisticsEnable bit in the MACCtrl register, and a logic 0 to the FramesXmtdOk bit within the StatisticsMask register.
3.2.1.13 FrameTooLongErrors Class............................. Ethernet MIB Statistics I/O Base Address ......... IoBaseAddress register value Memory Base Address . MemBaseAddress register value Address Offset .............. 0xC8 Default Value ................ 0x0000 Access Rule.................. Word Width ............................ 16 bits Bit 15..0 BIT Name FrameTooLongErrors BIT Description Type HW Reset SW Reset
Frame Too Long Errors is a count of frames R/W received whose length exceed the value in the MaxFrameSize register. FrameTooLongErrors will wrap around to zero after reaching 0xFFFF. See IEEE 802.3 Clause 30.3.1.1.25. An UpdateStats interrupt (UpdateStats bit within the IntStatus register) will occur when FrameTooLongErrors reaches a value of 0xC000. FrameTooLongErrors is enabled by writing a logic 1 to the StatisticsEnable bit in the MACCtrl register, and a logic 0 to the FrameTooLongErrors bit within the StatisticsMask register.
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IP1000A LF
Preliminary Data Sheet
3.2.1.14 InRangeLengthErrors Class............................. Ethernet MIB Statistics I/O Base Address ......... IoBaseAddress register value Memory Base Address . MemBaseAddress register value Address Offset .............. 0xCA Default Value ................ 0x0000 Access Rule.................. Word Width ............................ 16 bits Bit 15..0 BIT Name InRangeLength Errors BIT Description Type HW Reset SW Reset
In Range Length Errors is a count of the number R/W of frames with the Length/Type field value between the minimum unpadded MAC client data size and the maximum allowed MAC client data size, inclusive, that does not match the number of MAC client data octets received. InRangeLengthErrors also increments for frames whose Length/Type field value is less than the minimum allowed unpadded MAC client data size, and the number of MAC client data octets received is greater than the minimum unpadded MAC client data size. InRangeLengthErrors will wrap around to zero after reaching 0xFFFF. See IEEE 802.3 Clause 30.3.1.1.23. An UpdateStats interrupt (UpdateStats bit within the IntStatus register) will occur when InRangeLengthErrors reaches a value of 0xC000. InRangeLengthErrors is enabled by writing a logic 1 to the StatisticsEnable bit in the MACCtrl register, and a logic 0 to the InRangeLengthErrors bit within the StatisticsMask register.
3.2.1.15 LateCollisions Class............................. Ethernet MIB Statistics I/O Base Address ......... IoBaseAddress register value Memory Base Address . MemBaseAddress register value Address Offset .............. 0xE8 Default Value ................ 0x00000000 Access Rule.................. Double Word Width ............................ 32 bits Bit 31..0 BIT Name LateCollisions BIT Description Type HW Reset SW Reset
Late Collisions is a count of the number of times R/W that a collision has been detected later than 1 slot time into the transmitted frame. LateCollisions will wrap around to zero after reaching 0xFFFFFFFF. See IEEE 802.3 Clause 30.3.1.1.10. An UpdateStats interrupt (UpdateStats bit within the IntStatus register) will occur when
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Preliminary Data Sheet
BIT Name BIT Description LateCollisions reaches a value of 0xC0000000. LateCollisions is enabled by writing a logic 1 to the StatisticsEnable bit in the MACCtrl register, and a logic 0 to the LateCollisions bit within the StatisticsMask register. Type HW Reset SW Reset
Bit
3.2.1.16 MacControlFramesRcvd Class............................. Ethernet MIB Statistics I/O Base Address ......... IoBaseAddress register value Memory Base Address . MemBaseAddress register value Address Offset .............. 0xC6 Default Value ................ 0x0000 Access Rule.................. Word Width ............................ 16 bits Bit 15..0 BIT Name MacControlFramesRcvd BIT Description Type HW Reset SW Reset
MAC Control Frames Received is a count of the R/W number of MAC control PAUSE frames, and only PAUSE frames, received successfully. MacControlFramesRcvd will wrap around to zero after reaching 0xFFFF. An UpdateStats interrupt (UpdateStats bit within the IntStatus register) will occur when MacControlFramesRcvd reaches a value of 0xC000. MacControlFramesRcvd is enabled by writing a logic 1 to the StatisticsEnable bit in the MACCtrl register, and a logic 0 to the MacControlFramesRcvd bit within the StatisticsMask register.
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Preliminary Data Sheet
3.2.1.17 MacControlFramesXmtd Class............................. Ethernet MIB Statistics I/O Base Address ......... IoBaseAddress register value Memory Base Address . MemBaseAddress register value Address Offset .............. 0xFA Default Value ................ 0x0000 Access Rule.................. Word Width ............................ 16 bits Bit 15..0 BIT Name MacControlFramesXmtd BIT Description Type HW Reset SW Reset
MAC Control Frames Transmitted is the count of R/W MAC control frames transmitted by the IP1000A LF. Note, acControl-FramesXmtd does not include MAC control frames transferred to the IP1000A LF by the host system via the transmit DMA process. An UpdateStats interrupt (UpdateStats bit within the IntStatus register) will occur when MacControlFramesXmtd reaches a value of 0xC000. MacControlFramesXmtd is enabled by writing a logic 1 to the StatisticsEnable bit in the MACCtrl register, and a logic 0 to the MacControlFramesXmtd bit within the StatisticsMask register.
3.2.1.18 McstFramesRcvdOk Class............................. Ethernet MIB Statistics I/O Base Address ......... IoBaseAddress register value Memory Base Address . MemBaseAddress register value Address Offset .............. 0xB8 Default Value ................ 0x00000000 Access Rule.................. Double Word Width ............................ 32 bits Bit 31..0 BIT Name BIT Description Type HW Reset SW Reset
McstFramesRcvd Broadcast Frames Received OK is the count of the R/W Ok number of frames that are successfully received to a group destination address other than the broadcast address (0xFFFFFFFFFFFF). McstFramesRcvdOk does not include frames received with frames too long, FCS, length or alignment errors, or frames lost due to internal MAC sublayer error (i.e. overrun). McstFramesRcvdOk will wrap around to zero after reaching 0xFFFFFFFF. See IEEE 802.3 Clause 30.3.1.1.21. An UpdateStats interrupt (UpdateStats bit within the IntStatus register) will occur when McstFramesRcvdOk reaches a value of 0xC0000000. McstFramesRcvdOk is enabled by writing a logic 1 to the StatisticsEnable bit in the
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IP1000A LF
Preliminary Data Sheet
BIT Name BIT Description MACCtrl register, and a logic 0 to the McstFramesRcvdOk bit within the StatisticsMask register. Type HW Reset SW Reset
Bit
3.2.1.19 McstFramesXmtdOk Class............................. Ethernet MIB Statistics I/O Base Address ......... IoBaseAddress register value Memory Base Address . MemBaseAddress register value Address Offset .............. 0xE0 Default Value ................ 0x00000000 Access Rule.................. Double Word Width ............................ 32 bits Bit 31..0 BIT Name BIT Description Type HW Reset SW Reset
McstFramesXmtd Multicast Frames Transmitted OK is a count of the R/W Ok number of frames that are successfully transmitted to a group destination address other than the broadcast address (0xFFFFFFFFFFFF). McstFramesXmtdOk will wrap around to zero after reaching 0xFFFFFFFF. See IEEE 802.3 Clause 30.3.1.1.18. An UpdateStats interrupt (UpdateStats bit within the IntStatus register) will occur when McstFramesXmtdOk reaches a value of 0xC0000000. McstFramesXmtdOk is enabled by writing a logic 1 to the StatisticsEnable bit in the MACCtrl register, and a logic 0 to the McstFramesXmtdOk bit within the StatisticsMask register.
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IP1000A LF
Preliminary Data Sheet
3.2.1.20 McstOctetRcvdOk Class............................. Ethernet MIB Statistics I/O Base Address ......... IoBaseAddress register value Memory Base Address . MemBaseAddress register value Address Offset .............. 0xAC Default Value ................ 0x00000000 Access Rule.................. Double Word Width ............................ 32 bits Bit 31..0 BIT Name BIT Description Type HW Reset SW Reset
McstOctetRcvdOk Multicast Octets Received OK is the count of the R/W number of data and padding octets in frames, to a group destination address other than the broadcast address (0xFFFFFFFFFFFF), that are successfully received. McstOctetRcvdOk does not include frames received with frames too long, FCS, length or alignment errors, or frames lost due to internal MAC sublayer error (i.e. overrun). McstOctetRcvdOk will wrap around to zero after reaching 0xFFFFFFFF. All IP1000A LF byte and octet count based statistic registers include the VLAN tag (4 octets) regardless of whether or not the IP1000A LF is adding (on frame transmission) or removing (on frame reception) the VLAN tag automatically. An UpdateStats interrupt (UpdateStats bit within the IntStatus register) will occur when McstOctetRcvdOk reaches a value of 0xC0000000. McstOctetRcvdOk is enabled by writing a logic 1 to the StatisticsEnable bit in the MACCtrl register, and a logic 0 to the McstOctetRcvdOk bit within the StatisticsMask register.
3.2.1.21 McstOctetXmtOk Class............................. Ethernet MIB Statistics I/O Base Address ......... IoBaseAddress register value Memory Base Address . MemBaseAddress register value Address Offset .............. 0xD4 Default Value ................ 0x00000000 Access Rule.................. Double Word Width ............................ 32 bits Bit 31..0 BIT Name BIT Description Type HW Reset SW Reset
McstOctetXmtOk Multicast Octets Transmitted OK is a count of data R/W and padding octets of frames successfully transmitted to a group destination address other than the broadcast address (0xFFFFFFFFFFFF). McstOctetXmtOk will wrap around to zero after
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IP1000A LF
Preliminary Data Sheet
BIT Name BIT Description reaching 0xFFFFFFFF. All IP1000A LF byte and octet count based statistic registers include the VLAN tag (4 octets) regardless of whether or not the IP1000A LF is adding (on frame transmission) or removing (on frame reception) the VLAN tag automatically. An UpdateStats interrupt (UpdateStats bit within the IntStatus register) will occur when McstOctetXmtOk reaches a value of 0xC0000000. McstOctetXmtOk is enabled by writing a logic 1 to the StatisticsEnable bit in the MACCtrl register, and a logic 0 to the McstOctetXmtOk bit within the StatisticsMask register. Type HW Reset SW Reset
Bit
3.2.1.22 MultiColFrames Class............................. Ethernet MIB Statistics I/O Base Address ......... IoBaseAddress register value Memory Base Address . MemBaseAddress register value Address Offset .............. 0xEC Default Value ................ 0x00000000 Access Rule.................. Double Word Width ............................ 32 bits Bit 31..0 BIT Name MultiColFrames BIT Description Multiple Collision Frames is a count of the number of frames that are involved in more than one collision and are subsequently transmitted successfully. MultiColFrames will wrap around to zero after reaching 0xFFFFFFFF. See IEEE 802.3 Clause 30.3.1.1.4. An UpdateStats interrupt (UpdateStats bit within the IntStatus register) will occur when MultiColFrames reaches a value of 0xC0000000. MultiColFrames is enabled by writing a logic 1 to the StatisticsEnable bit in the MACCtrl register, and a logic 0 to the MultiColFrames bit within the StatisticsMask register. Type R/W HW Reset SW Reset
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IP1000A LF
Preliminary Data Sheet
3.2.1.23 OctetRcvOk Class............................. Ethernet MIB Statistics I/O Base Address ......... IoBaseAddress register value Memory Base Address . MemBaseAddress register value Address Offset .............. 0xA8 Default Value ................ 0x00000000 Access Rule.................. Double Word Width ............................ 32 bits Bit 31..0 BIT Name OctetRcvOk BIT Description Type HW Reset SW Reset
Octets Received OK is the count of the number of R/W data and padding octets in frames that are successfully received. OctetRcvOk does not include frames received with frames too long, FCS, length or alignment errors, or frames lost due to internal MAC sublayer error (i.e. overrun). OctetRcvOk will wrap around to zero after reaching 0xFFFFFFFF. See IEEE 802.3 Clause 30.3.1.1.14. All IP1000A LF byte and octet count based statistic registers include the VLAN tag (4 octets) regardless of whether or not the IP1000A LF is adding (on frame transmission) or removing (on frame reception) the VLAN tag automatically. An UpdateStats interrupt (UpdateStats bit within the IntStatus register) will occur when OctetRcvOk reaches a value of 0xC0000000. OctetRcvOk is enabled by writing a logic 1 to the StatisticsEnable bit in the MACCtrl register, and a logic 0 to the OctetRcvOk bit within the StatisticsMask register.
3.2.1.24 OctetXmtOk Class............................. Ethernet MIB Statistics I/O Base Address ......... IoBaseAddress register value Memory Base Address . MemBaseAddress register value Address Offset .............. 0xD0 Default Value ................ 0x00000000 Access Rule.................. Double Word Width ............................ 32 bits Bit 31..0 BIT Name OctetXmtOk BIT Description Type HW Reset SW Reset
Octets Transmitted OK is a count of data and R/W padding octets of frames successfully transmitted. OctetXmtOk will wrap around to zero after reaching 0xFFFFFFFF. See IEEE 802.3 Clause 30.3.1.1.8. All IP1000A LF byte and octet count based statistic registers include the VLAN tag (4 octets) regardless of whether or not the IP1000A LF is
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IP1000A LF
Preliminary Data Sheet
BIT Name BIT Description adding (on frame transmission) or removing (on frame reception) the VLAN tag automatically. An UpdateStats interrupt (UpdateStats bit within the IntStatus register) will occur when OctetXmtOk reaches a value of 0xC0000000. OctetXmtOk is enabled by writing a logic 1 to the StatisticsEnable bit in the MACCtrl register, and a logic 0 to the OctetXmtOk bit within the StatisticsMask register. Type HW Reset SW Reset
Bit
3.2.1.25 SingleColFrames Class............................. Ethernet MIB Statistics I/O Base Address ......... IoBaseAddress register value Memory Base Address . MemBaseAddress register value Address Offset .............. 0xF0 Default Value ................ 0x00000000 Access Rule.................. Double Word Width ............................ 32 bits Bit 31..0 BIT Name BIT Description Type HW Reset SW Reset
SingleColFrames Single Collision Frames is a count of the number R/W of frames that are involved in a single collision, and are subsequently transmitted successfully. SingleColFrames will wrap around to zero after reaching 0xFFFFFFFF. See IEEE 802.3 Clause 30.3.1.1.3. An UpdateStats interrupt (UpdateStats bit within the IntStatus register) will occur when SingleColFrames reaches a value of 0xC0000000. SingleColFrames is enabled by writing a logic 1 to the StatisticsEnable bit in the MACCtrl register, and a logic 0 to the SingleColFrames bit within the StatisticsMask register.
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IP1000A LF
Preliminary Data Sheet
PCI Configuration Space Registers CapId0
3.2.2 3.2.2.1
Class............................. PCI Configuration Registers, Power Management I/O Base Address ......... PCI device configuration header start Address Offset .............. 0x50 Default Value ................ 0x01 Access Rule.................. Byte Width ............................ 8 bits Bit 7..0 BIT Name CapId BIT Description Capabilities ID. CapId indicates the type of the capability data structure for the IP1000A LF. CapId is set to the value 0x01 to indicate a PCI Power Management structure. Type R HW Reset SW Reset
3.2.2.2
CapId1
Class............................. PCI Configuration Registers, Power Management I/O Base Address ......... PCI device configuration header start Address Offset .............. 0x60 Default Value ................ 0x07 Access Rule.................. Byte Width ............................ 8 bits Bit 7..0 BIT Name CapId BIT Description Capabilities ID. CapId indicates the type of the capability data structure for the IP1000A LF. Type R HW Reset SW Reset
3.2.2.3
CapPtr
Class............................. PCI Configuration Registers I/O Base Address ......... PCI device configuration header start Address Offset .............. 0x34 Default Value ................ 0x50 Access Rule.................. Byte Width ............................ 8 bits Bit 7..0 BIT Name CapPtr BIT Description Capabilities Pointer. CapPtr indicates the beginning of a chain of registers which describe enhanced functions. CapPtr register returns 0x50, which is the address of the first in a series of power management registers. Type R HW Reset SW Reset
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IP1000A LF
Preliminary Data Sheet
ClassCode
3.2.2.4
Class............................. PCI Configuration Registers I/O Base Address ......... PCI device configuration header start Address Offset .............. 0x09 Default Value ................ 0x020000 Access Rule.................. Byte Width ............................ 24 bits Bit 23..0 BIT Name ClassCode BIT Description Class Code. ClassCode identifies the general function of the PCI device. A value of 0x020000 indicates an Ethernet network controller. Type R HW Reset SW Reset
3.2.2.5
ConfigCommand
Class............................. PCI Configuration Registers I/O Base Address ......... PCI device configuration header start Address Offset .............. 0x04 Default Value ................ 0x0000 Access Rule.................. Word Width ............................ 16 bits ConfigCommand provides control over the IP1000A LF's ability to generate and respond to PCI cycles. When ConfigCommand is a logic 0, the IP1000A LF is logically disconnected from the PCI bus, except for configuration cycles. Bit 0 BIT Name IoSpace BIT Description I/O Space. When IoSpace is a logic the IP1000A LF can respond to I/ O space accesses (if the IP1000A LF is in the D0 power state). Memory Space. When MemorySpace, and the AddressDecodeEnable bit in the ExpRomBaseAddress register are both a logic 1, and if the IP1000A LF is in the D0 power state, the IP1000A LF is able to decode accesses to an Expansion ROM (if present). Bus Master. When BusMaster is a logic 1 the IP1000A LF is able to initiate bus master cycles (if the adapter is in the D0 power state). Special Cycles. When SpecialCycles is a logic 0, the IP1000A LF ignores all Special Cycle operations. When SpecialCycles is a logic 1, the IP1000A LF can monitor Special Cycle operations. Memory Write and Invalidate Enable. When MWlEnable is a logic 1 the IP1000A LF is permitted to use the MWI command. Type R/W HW Reset SW Reset
1
MemorySpace
R/W
2
BusMaster
R/W
3
SpecialCycles
R
4
MWlEnable
R/W
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IP1000A LF
Preliminary Data Sheet
BIT Name BIT Description Type HW Reset SW Reset
Bit 5
VGAPaletteSnoop VGA Palette Snoop. VGAPaletteSnoop controls R how VGA compatible graphics devices handle accesses to VGA palette registers. When VGAPaletteSnoop is a logic 1, palette snooping is enabled (i.e., the device does not respond to palette reg-ister writes and snoops the data). When VGAPaletteSnoop is a logic 0, the device should treat palette write accesses like all other accesses. 6 ParityErrorResponse Parity Error Response. When ParityErrorResponse R/W is a logic 1 the IP1000A LF responds to parity errors as defined within the PCI specification. When ParityErrorResponse is a logic 0, the IP1000A LF ignores parity errors. 7 SteppingControl Stepping Control. SteppingControl determines R whether or not a device does address/data stepping. Devices that never do stepping must hardwire SteppingControl to a logic 0. Devices that always do stepping must hardwire SteppingControl to a logic 1. 8 SERREnable System Error Enable. When SERREnable is a R/W logic 1, the SERRN signal is allowed to transition as appropriate. When SERREnable is a logic 0, the SERRN signal is a continuous logic 0. 9 FastBack-to-Back Fast Back-to-Back Enable. FastBack-to-BackEnable R Enable controls whether or not a master can do fast back-to-back transactions to different devices. Initialization software will set FastBack-to-BackEnable if all targets are fast back-to-back capable. If Fast-Back-to-BackEnable is a logic 1, the master is allowed to generate fast back-to-back transactions to different agents. If FastBack-to-BackEnable is a logic 0, fast back-to-back transactions are only allowed to the same agent. 10 InterruptDisable Interrupt Disable. InterruptDisable disables the R/W IP1000A LF from asserting INTAN. If InterruptDisable is a logic 0, the IP1000A LF may assert the INTAN signal. If InterruptDisable is a logic 1, the IP1000A LF may not assert the INTAN signal. 15..11 Reserved Reserved for future use. Write as zero, ignore on read. N/A
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IP1000A LF
Preliminary Data Sheet
ConfigStatus
3.2.2.6
Class............................. PCI Configuration Registers I/O Base Address ......... PCI device configuration header start Address Offset .............. 0x06 Default Value ................ 0x0230 Access Rule.................. Word Width ............................ 16 bits ConfigStatus is used to record status information for PCI bus events. Read/write bits within ConfigStatus can only be set to a logic 0, not to a logic 1. Bits are set to a logic 0 by writing a logic 1 to the appropriate bit. Bit 2..0 3 BIT Name Reserved IntStatus BIT Description Reserved for future use. Write as zero, ignore on read. Interrupt Status. IntStatus reflects the state of the interrupt of the IP1000A LF. Only when the Interrupt Disable bit in the command register is a logic 0 and IntStatus is a logic 1, will the IP1000A LF's INTAN signal be asserted. Setting the Interrupt Disable bit to a 1 has no effect on the state of IntStatus. Capabilities List. CapabilitiesList is a logic 1 to indicate a set of extended capabilities registers exists for the IP1000A LF. The CapPtr register indicates the first address location of the extended capabilities register set. 66MHz Capable. When 66MHzCapable is a logic 1 operation of the IP1000A LF PCI bus interface at 66MHz is supported. Reserved for future use. Write as zero, ignore on read. Fast Back to Back. When FastBackToBack is a logic 1 the IP1000A LF when operating as a Target, supports fast back-to-back transactions as defined by the criteria in the section 3.4.2 of the PCI specification. Type N/A R HW Reset SW Reset
4
CapabilitiesList
R
5
66MHzCapable
R
6 7
Reserved FastBackToBack
N/A R
8
MasterDataParity Master Data Parity Error. When Error MasterDataParityError is a logic 1, the IP1000A LF when operating as a Master, has detected the PERRN signal asserted, and the ParityErrorResponse bit in the ConfigCommand register as a logic 1. Note: If the IP1000A LF is initialized to PCI-X mode, MasterDataPari-tyError is set in either the initiator or target under the following conditions: The initiator (requester) of a read transaction that is completed immediately calculates a data parity error. The initiator (requester) of a read transaction that is terminated with Split Response calculates a data parity error in the Split Response. The initiator (requester) of a write that is comleted immediately observes PERRN asserted three clocks after one or more of its data phases. The initiator (requester) of a write that is
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IP1000A LF
Preliminary Data Sheet
BIT Name BIT Description terminated with Split Response observes PERRN asserted three clocks after the data phase. The target (requester) of a Split Completion calculates a data parity error in either read data or a Split Completion Message. The target (requester) receives a Split Completion Message that indicates a data parity error occurred on one of this device's non-posted write transactions. Type HW Reset SW Reset
Bit
10..9
DevselTiming
11
SignaledTargetAbort
Device Select Timing. DevselTiming is used to encode the slowest time with which the IP1000A LF asserts the DEVSELN signal. A value of 0x1 for DevselTiming indicates support for "medium" speed DEVSELN assertion. Signaled Target Abort. The IP1000A LF sets SignaledTargetAbort to a logic 1 when the IP1000A LF terminates a bus transaction with target-abort. Received Target Abort. The IP1000A LF sets ReceivedTargetAbort to a logic 1 when, operating as a bus master, an IP1000A LF bus transaction is terminated with target-abort.
R
R
12
ReceivedTargetAbort
R
13
ReceivedMaster- Received Master Abort. The IP1000A LF sets Abort ReceivedMasterAbort to a logic 1 when, operating as a bus master, an IP1000A LF bus transaction is terminated with master-abort. SignaledSystem- Signaled System Error. When Error SignaledSystemError is a logic 1, the IP1000A LF asserts the SERRN signal. DetectedParityError Detected Parity Error. When DetectedParityError is a logic 1 the IP1000A LF has detected a parity error, regardless of whether parity error handling is enabled.
R
14
R
15
R
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IP1000A LF
Preliminary Data Sheet
Data
3.2.2.7
Class............................. PCI Configuration Registers I/O Base Address ......... PCI device configuration header start Address Offset .............. 0x57 Default Value ................ 0x0000 Access Rule.................. Byte Width ............................ 8 bits Bit 7..0 BIT Name Data BIT Description Data reports power consumption and dissipation of the IP1000A LF at worst case conditions. To properly interpret the value read from Data, it must be scaled by the factor indicated in the Data_Scale field of the PowerMgmtCtrl register. The value of Data depends on the value of the Data_Select field of the PowerMgmtCtrl register.. Data_Select 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 through 0xF 3.2.2.8 DeviceId Data 40*Data_Scale Watts D0 Power Consumption 40*Data_Scale Watts D1 Power Consumption 40*Data_Scale Watts D2 Power Consumption 40*Data_Scale Watts D3 Power Consumption 40*Data_Scale Watts D4 Power Consumption 40*Data_Scale Watts D5 Power Consumption 40*Data_Scale Watts D6 Power Consumption 40*Data_Scale Watts D7 Power Consumption 0x00 Reserved. Type R HW Reset SW Reset
Class............................. PCI Configuration Registers I/O Base Address ......... PCI device configuration header start Address Offset .............. 0x02 Access Rule.................. Word Default Value ................ 0x1023 Width ............................ 16 bits Bit 15..0 BIT Name DeviceId BIT Description Type HW Reset SW Reset
Device ID. DeviceId contains the 16-bit device R/W identifier for the IP1000A LF. The DeviceId may also be modified using the ForcedConfig[1..0] bits in the AsicCtrl register.
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IP1000A LF
Preliminary Data Sheet
ExpRomBaseAddress
3.2.2.9
Class............................. PCI Configuration Registers, Configuration I/O Base Address ......... PCI device configuration header start Address Offset .............. 0x30 Default Value ................ 0x00000000 Access Rule.................. Double Word Width ............................ 0x32 ExpRomBaseAddress defines the base address for an Expansion ROM which may be interfaced to the IP1000A LF. Bit 0 BIT Name AddressDecodeEnable BIT Description Type HW Reset SW Reset
Address Decode Enable. When R/W AddressDecodeEnable is a logic 0 accesses to an Expansion ROM are disabled. When AddressDecodeEnable is a logic 1 and the MemorySpace bit in the ConfigCommand register is also a logic 1, accesses to an Expansion ROM are enabled. Reserved for future use. Write as zero, ignore on read. N/A R/W
14..1
Reserved
31..15 RomBaseAddress ROM Base Address. RomBaseAddress contains the expansion ROM base address, or the upper 16 bits (or 15 bits, depending on the state of the ExpRomSize bit in the AsicCtrl register) of the Expansion ROM address range. If the ExpRomSize bit in the AsicCtrl register is a logic 0, all 16 bits of RomBaseAddress are valid. If the ExpRomSize bit in the AsicCtrl register is a logic 1, bits 31 through 16 of RomBaseAddress are valid, with bit 15 ignored (set to a logic 0) during write operations.
3.2.2.10 HeaderType Class............................. PCI Configuration Registers I/O Base Address ......... PCI device configuration header start Address Offset .............. 0x0E Default Value ................ 0x00 Access Rule.................. Byte Width ............................ 8 bits Bit 7..0 BIT Name HeaderType BIT Description Header Type. HeaderType is set to 0x00 identifying the IP1000A LF as a single-function PCI device and specifying the configuration register layout. Type R HW Reset SW Reset
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IP1000A LF
Preliminary Data Sheet
3.2.2.11 InterruptLine Class............................. PCI Configuration Registers I/O Base Address ......... PCI device configuration header start Address Offset .............. 0x3C Default Value ................ 0x00 Access Rule.................. Byte Width ............................ 8 bits Bit 7..0 BIT Name InterruptLine BIT Description Type HW Reset SW Reset
Interrupt Line. InterruptLine specifies the interrupt R/W level used by the IP1000A LF. By setting InterruptLine the host system may configure the appropriate interrupt vector for its Interrupt Service Routine. For 80x86 processor based host systems, InterruptLine corresponds to the IRQ number (0x00 through 0x0F), with the value 0xFF corresponding to disabled interrupts.
3.2.2.12 InterruptPin Class............................. PCI Configuration Registers I/O Base Address ......... PCI device configuration header start Address Offset .............. 0x3D Default Value ................ 0x01 Access Rule.................. Byte Width ............................ 8 bits Bit 7..0 BIT Name InterruptPin BIT Description Interrupt Pin. InterruptPin indicates which PCI interrupt signal the IP1000A LF will utilize. The IP1000A LF always utilizes the INTAN interrupt signal, corresponding to an InterruptPin value of 0x01. Type R HW Reset SW Reset
3.2.2.13 IoBaseAddress Class............................. PCI Configuration Registers I/O Base Address ......... PCI device configuration header start Address Offset .............. 0x10 Default Value ................ 0x00000000 Access Rule.................. Double Word Width ............................ 32 bits The host uses IoBaseAddress to define the I/O base address for the IP1000A LF. PCI system requires that I/O base addresses be set as if the host system used 32-bit I/O addressing. The upper 24 bits of IoBaseAddress are accessible, indicating that the IP1000A LF requires 256 bytes in the host system I/O address space. When AsicCtrlRegister ForcedConfig[0] is 1, the IP1000A LF is in ForcedConfig Mode. In this mode, the IO Base Address is loaded from EEPROM at offset 04'h(Upper Bytes), 05'h.
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IP1000A LF
Preliminary Data Sheet
BIT Name IoBaseAddrInd BIT Description I/O Base Address Indicator. When IoBaseAddrInd is a logic 1, IoBaseAddress contains the valid I/O base address for the IP1000A LF. Reserved for future use. Write as zero, ignore on read. I/O Base Address. IoBaseAddress contains the 24 bit I/O base address value. With 24 bits, the IP1000A LF uses 256 bytes of I/O address space. Type R/W HW Reset SW Reset
Bit 0
7..1 31..8
Reserved IoBaseAddress
N/A R/W
3.2.2.14 LatencyTimer Class............................. PCI Configuration Registers I/O Base Address ......... PCI device configuration header start Address Offset .............. 0x0D Default Value ................ 0x00 Access Rule.................. Byte Width ............................ 8 bits Bit 2..0 7..3 BIT Name Reserved LatencyTimer BIT Description Reserved for future use. Write as zero, ignore on read. Type N/A HW Reset SW Reset
Latency Timer. LatencyTimer indicates, in R/W increments of 8 bus clocks, the length of time which the IP1000A LF may hold the PCI bus in the presence of other bus requestors. Whenever the IP1000A LF asserts the FRAMEN signal, the latency timer is started. When the latency timer count expires, the IP1000A LF must relinquish the bus as soon as its GNTN signal has been de-asserted.
3.2.2.15 MaxLat Class............................. PCI Configuration Registers, Configuration I/O Base Address ......... PCI device configuration header start Address Offset .............. 0x3F Default Value ................ 0x0A Access Rule.................. Byte Width ............................ 8 bits Bit 7..0 BIT Name MaxLat BIT Description Maximum Latency. MaxLat specifies, in 250 ns increments, how often the IP1000A LF requires bus access while operating as a bus master. Bits 5 through 1 of the MaxLat value are loaded from the ConfigParm field within an EEPROM during auto initialization of the IP1000A LF. Type R HW Reset SW Reset
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IP1000A LF
Preliminary Data Sheet
3.2.2.16 MemBaseAddress Class............................. PCI Configuration Registers I/O Base Address ......... PCI device configuration header start Address Offset .............. 0x14 Default Value ................ 0x00000000 Access Rule.................. Double Word Width ............................ 32 bits MemBaseAddress can be disabled via loading of the ConfigParm field from an EEPROM during auto-iniTialization of the IP1000A LF. When AsicCtrlRegister ForcedConfig[0] is 1, the IP1000A LF is in ForcedConfig Mode. In this mode, the MemBase Address is loaded from EEPROM at offset 04'h(Upper Bytes), 05'h, the same as IO BaseAddress. Bit 0 BIT Name BIT Description Type HW Reset SW Reset
2..1
MemBaseAddrInd Memory Base Address Indicator. When R/W MemBaseAddrInd is a logic 1, MemBaseAddress contains the valid memory base address. MemMapType Memory Map Type. MemMapType defines how the host system maps the IP1000A LF's registers within the host system memory space. Bit 2 of MemMapType is always a logic 0, while bit 1 is loaded from the Lower1Meg bit of the ConfigParm field within an EEPROM during auto initialization of the IP1000A LF. BIT 2 0 0 1 BIT 1 REGISTER MAPPING 0 Anywhere within a 32 bit address space 1 Lower 1 megabyte of 32 bit address space x Undefined
7..3 31..8
Reserved Reserved for future use. Write as zero, ignore on read. N/A MemBaseAddress Memory Base Address. MemBaseAddress contains R/W the 24 bit memory base address value. With 24 bits, the IP1000A LF uses 256 bytes of I/O space.
3.2.2.17 MinGnt Class............................. PCI Configuration Registers I/O Base Address ......... PCI device configuration header start Address Offset .............. 0x3E Default Value ................ 0x50 Access Rule.................. Byte Width ............................ 8 bits Bit 7..0 BIT Name MinGnt BIT Description Minimum Grant Time. MinGnt specifies, in 250 ns increments, how long a burst period the IP1000A LF requires when operating as a bus master. Bits 7 through 4 of the MinGnt value are loaded from the ConfigParm field within an EEPROM during auto initialization of the IP1000A LF.
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Type R
HW Reset
SW Reset
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IP1000A LF
Preliminary Data Sheet
3.2.2.18 NextItemPtr0 Class............................. PCI Configuration Registers I/O Base Address ......... PCI device configuration header start Address Offset .............. 0x51 Default Value ................ 0x60 Access Rule.................. Byte Width ............................ 8 bits Bit 7..0 BIT Name NextItemPtr BIT Description Next Item Pointer. NextItemPtr indicates the next capability data structure in the capabilities list. When NextItemPtr is set to the value 0x00, there are no further data structures. Type R HW Reset SW Reset
3.2.2.19 NextItemPtr1 Class............................. PCI Configuration Registers I/O Base Address ......... PCI device configuration header start Address Offset .............. 0x61 Default Value ................ 0x00 Access Rule.................. Byte Width ............................ 8 bits Bit 7..0 BIT Name NextItemPtr BIT Description Next Item Pointer. NextItemPtr indicates the next capability data structure in the capabilities list. When NextItemPtr is set to the value 0x00, there are no further data structures. Type R HW Reset SW Reset
3.2.2.20 PowerMgmtCap Class............................. PCI Configuration Registers I/O Base Address ......... PCI device configuration header start Address Offset .............. 0x52 Default Value ................ 0x7602 Access Rule.................. Word Width ............................ 16 bits Bit 2..0 8..3 9 BIT Name Version Reserved D1Support BIT Description Version. Version is set to 0x2, indicating PCI Bus Power Management Specification Revision 1.1. Reserved for future use. Write as zero, ignore on read. D1 Power State Support. When D1Support is a logic 1, the IP1000A LF supports the D1 power state (see section 2.2.5.1). D1Support is loaded from the ConfigParm field of an EEPROM during auto initialization of the IP1000A LF.
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Type R N/A R
HW Reset
SW Reset
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IP1000A LF
Preliminary Data Sheet
BIT Name D2Support BIT Description D2 Power State Support. When D2Support is a logic 1, the IP1000A LF supports the D2 power state (see section 2.2.5.1). D2Support is loaded from the ConfigParm field of an EEPROM during auto initialization of the IP1000A LF. Power Management Event Support. PmeSupport indicates the power states from which the IP1000A LF is able to generate a power management event by asserting the PMEN signal. Each bit corresponds to a power state. A logic 1 in a particular bit position indicates that evens can be generated from the indicated power state. PmeSupport bits 14 and 11 are always set to a logic 1 while bits 12, 13, and 15 are loaded from the ConfigParm field of an EEPROM during auto initialization of the IP1000A LF. Type R HW Reset SW Reset
Bit 10
15..11 PmeSupport
R
3.2.2.21 PowerMgmtCtrl Class............................. PCI Configuration Registers I/O Base Address ......... PCI device configuration header start Address Offset .............. 0x54 Default Value ................ 0x4000 Access Rule.................. Word Width ............................ 16 bits Bit 1..0 BIT Name PowerState BIT Description Type HW Reset SW Reset
Power State. PowerState indicates the current R/W power state of the IP1000A LF. If PowerState is set to a value other than 0x0, the IP1000A LF will not respond to PCI I/O or memory cycles, nor will the IP1000A LF be able to generate PCI bus master cycles. BIT 1 0 0 1 1 BIT 0 0 1 0 1 POWER STATE D0 D1 D2 D3 N/A
7..2 8
Reserved PmeEn
Reserved for future use. Write as zero, ignore on read.
Power Management Event Enable. When PmeEn R/W is a logic 1, the IP1000A LF is allowed to report wake events on the PMEN signal. The criteria for generating wake events is defined by the WakeEvent register. PmeEn is loaded from the ConfigParm field of an EEPROM during auto initialization of the IP1000A LF.
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IP1000A LF
Preliminary Data Sheet
BIT Name Data_Select BIT Description Data Select is used to select which data is to be reported through the Data register and Data_Scale field. Data Scale Only indicates the scaling factor to be used when interpreting the value of the Data register. The interpretation of the scale values is defined as follows: DATA_SCALE 0x0 0x1 0x2 0x3 SCALE FACTOR Unknown 0.1 0.01 0.001 Type R/W HW Reset SW Reset
Bit 12..9
14..13 Data_Scale
R
15
PmeStatus
Power Management Event Status. When R/W PmeStatus is a logic 1 a wake event has occurred. PmeStatus may be a logic 1 regardless of the value of PmeEn. Writing a logic 1 to PmeStatus will set PmeStatus to a logic 0. Writing a logic 0 to PmeStatus has no effect.
3.2.2.22 RevisionId Class............................. PCI Configuration Registers I/O Base Address ......... PCI device configuration header start Address Offset .............. 0x08 Default Value ................ Depends on revision of actual device. See description below. Access Rule.................. Byte Width ............................ 8 bits Bit 7..0 BIT Name RevisionId BIT Description Revision ID= 41. RevisionId contains a revision code for the IP1000A LF. Type R HW Reset SW Reset
3.2.2.23 SubsystemId Class............................. PCI Configuration Registers I/O Base Address ......... PCI device configuration header start Address Offset .............. 0x2E Default Value ................ 0x0000 Access Rule.................. Byte Width ............................ 16 bits Bit 15..0 BIT Name SubsystemId BIT Description Subsystem ID. SubsystemId contains the value loaded from the ConfigParm field within an EEPROM during auto initialization of the IP1000A LF.
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Type R
HW Reset
SW Reset
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IP1000A LF
Preliminary Data Sheet
SubsystemVendorId Class............................. PCI Configuration Registers I/O Base Address ......... PCI device configuration header start Address Offset .............. 0x2C Default Value ................ 0x0000 Access Rule.................. Word Width ............................ 16 bits Bit 15..0 BIT Name BIT Description Type R HW Reset SW Reset
SubsystemVendorId Subsystem Vendor ID. SubsystemVendorId contains the value loaded from the ConfigParm field within an EEPROM during auto initialization of the IP1000A LF.
3.2.2.24 VendorId Class............................. PCI Configuration Registers I/O Base Address ......... PCI device configuration header start Address Offset .............. 0x00 Default Value ................ 0x13F0 Access Rule.................. Word Width ............................ 16 bits Bit 15..0 BIT Name VendorId BIT Description Vendor ID. VendorId contains the unique 16-bit manufacturer's ID as indicated by the PCI Special Interest Group. The manufacturer ID is 0x13F0. Type R HW Reset SW Reset
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IP1000A LF
Preliminary Data Sheet
EEPROM Fields
3.2.3
Table 3-4 summarizes the layout of the data stored in an EEPROM connected to the IP1000A LF. Most defined EEPROM fields are read from the EEPROM and loaded into unique register bit positions within the IP1000A LF during auto initialization. In Table 3-4, all locations marked "Unused" and all locations not shown are not utilized by the IP1000A LF. Table 3-4 : IP1000A LF EEPROM Field Layout 16 BIT WORD StationAddress StationAddress StationAddress Unused Unused Unused Unused Unused Unused Unused Unused Unused LEDMode PCI Register I/O, Mem Base[31:16] PCI Register I/O, I/O, Mem Base[15:8] SubsystemId SubsystemVendorId AsicCtrl ConfigParm ADDR OFFSET 12 11 10 F E D C B A 9 8 7 6 5 4 3 2 1 0
3.2.3.1
ConfigParm
Class............................. EEPROM Fields I/O Base Address ......... 0x00, accessed via the EepromCtrl register Address Offset .............. 0x00 Access Rule.................. Word Width ............................ 16 bits Bit 0 1 BIT Name FastBackToBack Lower1Meg BIT Description Fast Back to Back. FastBackToBack corresponds to the FastBackTo-Back bit of the ConfigStatus register. Lower 1 Megabyte. Lower1Meg corresponds to bit 1 of the MemMap-Type field in the MemBaseAddress register.
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IP1000A LF
Preliminary Data Sheet
BIT Name BIT Description DisableMemBase Disable Memory Base Address Register. DisableMemBase does not correspond directly to any register accessible by the host system. If DisableMemBase is a logic 1 during auto initialization of the IP1000A LF, the MemBaseAddress register will be disabled. When disabled, the value returned when the MemBaseAddress register is read is undefined. D3ColdPme D3 Cold Power Management Event. D3ColdPme corresponds to bit 15 of the PmeSupport field within the PowerMgmtCap register. D1Support D1 Power State Support. D1Support corresponds to the D1Support bit of the PowerMgmtCap register, and bit 12 of the PmeSupport field within the PowerMgmtCap register. D2 Power State Support. D2Support corresponds to the D2Support bit of the PowerMgmtCap register, and bit 13 of the PmeSupport field within the PowerMgmtCap register. Power Management Event Enable. PmeEn corresponds to the PmeEn bit in the PowerMgmtCtrl register. Minimum Grant. MinGnt corresponds to bits 7 through 4 of the MinGnt register. Maximum Latency. MaxLat corresponds to bits 5 through 1 of the Max-Lat register.
Bit 2
3 4
5
D2Support
6 10..7
PmeEn MinGnt
15..11 MaxLat
3.2.3.2
AsicCtrl
Class............................. EEPROM Fields I/O Base Address ......... 0x00, accessed via the EepromCtrl register Address Offset .............. 0x01 Access Rule.................. Word Width ............................ 16 bits ASIC Control supplies the value for several bits of the AsicCtrl register and the WakeEvent register. Bit 0 1 2 3 4 5 6 7 8 14..9 15 BIT Name BIT Description
Exp-ROMDisable 0: Enable Exp-ROM. (Default) 1: Disable Exp-ROM. Reserved Reserved Reserved PhySpeed10 PhySpeed100 PhySpeed1000 Reserved Reserved for future use. Reserved for future use. Write as zero, ignore on read. Reserved for future use. Write as zero, ignore on read. Physical Layer Device Speed 10. PhySpeed10 corresponds to the PhySpeed10 bit in the AsicCtrl register. Physical Layer Device Speed 100. PhySpeed100 corresponds to the PhySpeed100 bit in the AsicCtrl register. Physical Layer Device Speed 1000. PhySpeed1000 corresponds to the PhySpeed1000 bit AsicCtrl register. Reserved for future use.
ForcedConfigMode 0: Enable EEPROM (Default) 1: Disable EEPROM Reserved WakeOnLanPolarity Reserved for future use. Write as zero, ignore on read. Wake-On-LAN Polarity. WakeOnLanPolarity WakeOnLanEnable bit in the WakeEvent register.
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IP1000A LF
Preliminary Data Sheet
SubsystemVendorId
3.2.3.3
Class............................. EEPROM Fields I/O Base Address ......... 0x00, accessed via the EepromCtrl register Address Offset .............. 0x02 Access Rule.................. Word Width ............................ 16 bits Bit 15..0 BIT Name BIT Description corresponds to the
SubsystemVendorId Subsystem Vendor ID. SubsystemVendorId SubsystemVendorId register.
3.2.3.4
SubsystemId
Class............................. EEPROM Fields I/O Base Address ......... 0x00, accessed via the EepromCtrl register Address Offset .............. 0x03 Access Rule.................. Word Width ............................ 16 bits Bit 15..0 BIT Name SubsystemId BIT Description Subsystem ID. SubsystemId corresponds to the SubsystemId register.
3.2.3.5
PCI IO/Mem Base Address [15:8]
Class............................. EEPROM Fields I/O Base Address ......... 0x00, accessed via the EepromCtrl register Address Offset .............. 0x04 Access Rule.................. Word Width ............................ 16 bits Bit 0 7..1 15..8 BIT Name APS Reserved BIT Description Default setting as 1 Reserved for future use.
PCI IO/Mem Base At ForcedConfig Mode, PCI IO/Mem Base Address[15:8] are setted from the Address[15:8] field.
3.2.3.6
PCI IO/Mem Base Address [31:16]
Class............................. EEPROM Fields I/O Base Address ......... 0x00, accessed via the EepromCtrl register Address Offset .............. 0x05 Access Rule.................. Word Width ............................ 16 bits Bit 15..0 BIT Name BIT Description PCI IO/Mem Base At ForcedConfig Mode, PCI IO/Mem Base Address[31:16] are setted from Address[31:16] the field.
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IP1000A LF
Preliminary Data Sheet
LEDMode
3.2.3.7
Class............................. EEPROM Fields I/O Base Address ......... 0x00, accessed via the EepromCtrl register Address Offset .............. 0x06 Access Rule.................. Word Width ............................ 16 bits Bit 1:0 BIT Name LED Mode BIT Description BIT 1 0 0 1 1 BIT 0 0 1 0 1 LED MODE LED MODE 0 LED MODE 1 (default) LED MODE 2 LED MODE 3
LEDMode is used to control the LED signal pin (LEDLNK10N, LEDLNK100N, LEDLNK1000N, LEDDPLXN, LEDPWRN) functionality. Pin LED10N LED100N LED1000N LEDDPLXN LEDMode=1(default) Light_on= 10 link up Light_off= 10 link down Light_on = 100 link up Light_off = 100 link down Light_on = 1000 link up Light_off = 1000 link down Light_on = Full duplex Light_off= Half duplex Blink = Collision Light_off= not receiving Light_on = receiving Light_off= not transmitting Light_on = transmitting Blink(00) = activity LEDMode=0 {LED100,LED10}= on,on = speed1000 on,off = speed100 off,on = speed10 off,off= link down Light_on = link up (any speed) Light_off=link down(any speed) Light_on = Full duplex Light_off= Half duplex Light_on= link up Light_off= link down Blink = receiving Light_on= link up Light_off= link down Blink = activity LEDMode=2 Light_off= 10 link up Blink slow = 100 link up Light_on= 1000 link up Light on = 100 link up
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LEDRXN LEDTXN
Pin LED10N, LED100N
LED1000N LEDDPLXN LEDRXN
LEDTXN
Pin LED10N
LED100N
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IP1000A LF
Preliminary Data Sheet
BIT Name BIT Description Light_off = 100 link down Blink = activity Light_on = 1000 link up Light_off = 1000 link down Blink = activity Light_on = Full duplex Light_off= Half duplex Blink = Collision Light_on= 10 link up Light_off= 10 link down Blink = activity Light_on= link up Light_off= link down Blink = activity
Bit
LED1000N
LEDDPLXN
LEDRXN
LEDTXN
2 3
LED_Stat_Mode LED_Speed
4 5 6 15..7 3.2.3.8
DSPSetting DSPSetting DSPSetting Reserved StationAddress
LEDMode=3 In LEDMode3, IP1000A LF uses bi-color LED to display speed information. {LED100,LED10}= off,on = speed1000 on,off = speed100 off,off = speed10 LED1000N Light_on = link up Light_off = link down LEDDPLXN Light_on = Full duplex Light_off= Half duplex LEDRXN Light_on= link up Light_off= link down Blink = receiving LEDTXN Light_on= link up Light_off= link down Blink = activity Reserved. Default setting as 0. The Bits decide LED Flashing Speed 0: Light: 20ms, Dark: 80ms(Slow) 1: Light: 40ms, Dark: 160ms(Fast) Default setting as 0. Default setting as 0. Default setting as 1. Reserved for future use.
Pin LED10N, LED100N
Class............................. EEPROM Fields I/O Base Address ......... 0x00, accessed via the EepromCtrl register Address Offset .............. 0x10 Access Rule.................. Byte Width ............................ 48 bits Bit 47..0 BIT Name StationAddress BIT Description Station Address. StationAddress corresponds to the StationAddress register.
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IP1000A LF
Preliminary Data Sheet
4
Absolute Maximum Ratings
Storage Temperature...................-65C to +150C Ambient Temperature ....................-65C to +70C Supply Voltage................................-0.3V to +3.6V Environmental stresses above those listed in Absolute Maximum Ratings may cause permanent damage resulting in device failure. Functionality at or above the limits listed below is not guaranteed. Exposure to the environmental stress at the levels listed below for extended periods may adversely affect device reliability.
5
Operating Ranges
Commercial Devices Temperature (T A ) .............................. 0C to +70C Supply Voltages (V CCH ) ..................... +3.3V 10% Supply Voltages (V CCL ) ....................... +1.8V 5% Input voltages .................................5V tolerant I/O Operating ranges define the limits of guaranteed device functionality.
6
DC Characteristics
DC characteristics are defined over commercial operating ranges unless specified otherwise. Operating Conditions Parameter Supply Voltage Supply Voltage Power Consumption Power Consumption Power Consumption Power Consumption Sym. VCC VCC_O Min. 1.73 3.135 Typ. 1.8 3.3 2.05 0.64 0.63 0.92 Max. 1.89 3.465 Unit V V W W W W Conditions
1000M full, VCC=1.8V, VCC_O=3.3V 100M full, VCC=1.8V, VCC_O=3.3V 10M full, VCC=1.8V, VCC_O=3.3V 10M idle, VCC=1.8V, VCC_O=3.3V
Power Consumption (without LED power consumption) Cable length 120m CAT5 Link Partner IP1000A LF Link condition Digital 1.8V Analog 1.8V Actual voltage 1.8V 1.8V 1000Mb Master 1000Mb D0 static 0.445A 0.197A 1000Mb D0 dynamic 0.450A 0.197A
CT 3.3V 3.3V 0.18A 0.18A
Digital 3.3V Analog 3.3V 3.3V 3.3V 0.02A 0.03A 0.07A 0.07A
Watt
2.05W 2.06W
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Preliminary Data Sheet
1000Mb Slave 1000Mb D0 static 1000Mb D0 dynamic 100Mb 100Mb D0 static 100Mb D0 dynamic 10Mb 10Mb D0 static 10Mb D0 dynamic No Link D0 Input Clock Parameter Frequency Frequency Tolerance
0.445A 0.449A 0.105A 0.108A 0.037A 0.037A 0.100A
0.197A 0.197A 0.048A 0.048A 0.000A 0.000A 0.101A
0.18A 0.18A 0.05A 0.05A 0.10A 0.10A 0.10A
0.02A 0.03A 0.03A 0.03A 0.03A 0.03A 0.03A
0.07A 0.07A 0.03A 0.03A 0.04A 0.04A 0.04A
2.05W 2.06W 0.64W 0.64W 0.63W 0.63W 0.92W
Sym.
Min. -50
Typ. 25
Max. +50
Unit MHz PPM
Conditions
I/O Electrical Characteristics Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Sym. VIL VIH VOL VOH Min. 2.0 0.4 2.4 Typ. Max. 0.8 Unit V V V V Conditions
IOH=4mA, VCC_O_x=3.3V IOL=4mA, VCC_O_x=3.3V
Parameter Symbol VCCH VCCL TTL I/O VIH VIL IIN IIN VOH VOH VOL VOL IOTS
Parameter Description 3.3V power supply voltage 1.8V power supply voltage Input high voltage(PCI Input Buffer 5V signalling) Input low voltage Input High leakage current Input Low leakage current Output high voltage TTL Output high voltage TTL Output low voltage PCI Output low voltage Output tri-state leakage
Test Conditions
Min 3.0 1.73
Typ
Max Unit 3.6 V 1.89 V 2 0.8 V V A A V V 0.4 V 0.55 V 10 A
VIN=2.7V VIN=0.5V IOH=-2mA IOH=-4mA IOL=4mA IOL=3mA 2.4 2.4
10 -10
TABLE 6-1 : DC Characteristics.
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Preliminary Data Sheet
7
Switching Characteristics
Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit
66 MHz PCI Interface Trc RSTN cycle Trr Rising Edge or RSTN to chip recovery Tcc Tch Tcl Trv Trvp Trzo Troz Tsu Tsup1 Tsup2 Thd Trstoff PCICLK cycle PCICLK high PCICLK low PCICLK rise to bused signal valid PCICLK rise to REQN, GNTN valid PCICLK rise to signal on PCICLK rise to signal off bused signal setup wrt PCICLK rise GNTN setup wrt PCICLK rise REQN setup wrt PCICLK rise signal hold wrt PCICLK rise RSTN low to output signal float
300 1 15 6 6 2 2 2 14 3 5 5 0 40 300 1 30 11 11 2 2 2 28 7 10 12 0 40 D.C. 25 11 12 6 6
ns s ns ns ns ns ns ns ns ns ns ns ns ns ns s ns ns ns ns ns ns ns ns ns ns ns ns MHz
33MHz PCI Interface Trc RSTN cycle Trr Tcc Tch Tcl Trv Trvp Trzo Troz Tsu Tsup1 Tsup2 Thd Trstoff Rising edge or RSTN to chip recovery PCICLK cycle PCICLK high PCICLK lwo PCICLK rise to bused signal valid PCICLK rise to REQN, GNTN valid PCICLK rise to signal on PCICLK rise to signal off Bused signal setup wrt PCICLK rise GNTN setup wrt PCICLK rise REQN setup wrt PCICLK rise Signal hold wrt PCICLK rise RSTN low to output signal float
Expansion Rom fC Clock Frequency for the following instructions: FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI, RDSR, WRSR fR tCH
1
Clock Frequency for READ instructions Clock High Time
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D.C. 18
20
MHz ns
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IP1000A LF
Preliminary Data Sheet
Parameter Description Clock Low Time Clock Slew Rate (peak to peak) S Active Setup Time (relative to C) S Not Active Hold Time (relative to C) Data In Setup Time Data In Hold Time S Active Hold Time (relative to C) S Not Active Setup Time (relative to C) S Deselect Time Output Disable Time Clock Low to Output Valid Output Hold Time HOLD Setup Time (relative to C) HOLD Hold Time (relative to C) HOLD Setup Time (relative to C) HOLD Hold Time (relative to C) HOLD to Output Low-Z HOLD to Output High-Z S High to Deep Power-down Mode S High to Standby Mode without Electronic Signature Read S High to Standby Mode with Electronic Signature Read Write Status Register Cycle Time Page Program Cycle Time Sector Erase Cycle Time Bulk Erase Cycle Time 1s 250 250 250 100 50 0 70 T=1 when 100Mb/s; 10 when 10Mb/s
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Parameter Symbol tCL1 tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tSHSL tSHQZ tCLQV tCLQX tHLCH tCHHH tHHCH tCHHL tHHQX2 tHLQZ2 tDP2 tRES12 tRES22 tW tPP tSE tBE
2
Test Conditions
Min 18 0.1 10 10 5 5 10 10 100
Typ
Max Unit ns V/ns ns ns ns ns ns ns ns 15 15 ns ns ns ns ns ns ns 15 20 3 3 1.8 ns ns s s s ms ms s s ns ns ns ns ns ns ns ns ns ns
0 10 10 10 10
5 2 2 3
15 5 3 6 500 500
EEPROM Interface Tskc EESK cycle Tskh Tskl Tcs Tpd Tcsk Tcsh Tdos Tdoh EESK high EESK low EECS low EEDI valid wrt EESK rise EECS setup wrt EESK rise EECS hold wrt EESK fall EEDO setup wrt EESK rise EEDO hold wrt EESK rise
MII Interface (10/100) - Transmit Tcc TXCLK cycle
40T
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IP1000A LF
Preliminary Data Sheet
Parameter Description TXCLK high TXCLK low TXCLK rise to TXD, TXEN valid TXD, TXEN hold after TXCLK rise T=1 when 100Mb/s; 10 when 10Mb/s Test Conditions Min 14T 14T 5 14T 14T 10 5 40T 26T 26T 20 Typ Max Unit 26T 26T 20 ns ns ns ns ns ns ns ns ns
Parameter Symbol Tch Tcl Trv Trh
MII Interface (10/100) - Receive Tcc RXCLK cycle Tch Tcl Tsu Thd RXCLK high RXCLK low RXD, RXER, RXDV setup wrt RXCLK rise RXD, RXER, RXDV hold wrt RXCLK rise
GMII Interface (1000) - Transmit Tcc GTXCLK cycle Tch GTXCLK high Tcl Trv Trh GTXCLK low GTXCLK rise to TXD, TXEN valid TXD, TXEN hold after GTXCLK rise
8 7.5 7.5 5 7.5 7.5 10 5 8 8.5 8.5 20 8.5 8.5 20
ns ns ns ns ns ns ns ns ns ns
GMII Interface (1000) - Receive Tcc RXCLK0 cycle Tch Tcl Tsu Thd RXCLK0 high RXCLK0 low RXD, RXER, RXDV setup wrt RXCLK0 rise RXD, RXER, RXDV hold wrt RXCLK0 rise
MII Interface - Management Tcc MDC cycle Tch MDC high Tcl Tsu Thd Trv MDC low MDIO setup wrt MDC rise MDIO hold wrt MDC rise MDC rise to MDIO valid
400 160 160 10 10 -
-
20
ns ns ns ns ns ns ns ns ns
MISC Interface Tcc CLK125 cycle Tch Tcl CLK125 high CLK125 low
8.0 4.0 4.0
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IP1000A LF
Preliminary Data Sheet
TABLE 7.1 : Switching Characteristics.
trc
RSTN
tcl
PCICLK trv BUSSED SIGNALS
tcc
tch
tsu
IP1000A LF
trvp
REQN
tsup2
trvp
GNTN
tsup1
trzo
ANY SIGNAL
thd
troz
trstoff
ANY SIGNAL
FIGURE 7-1: PCI Switching Characteristics
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IP1000A LF
Preliminary Data Sheet
tSHSL
S
tCHSL
tSLCH
tCHSH
tSHCH
C tDVCH tCHDX tCLCH tCHCL
D
MSB IN
LSB IN
Q
S
High Impedance
tHLCH tCHHL C tCHHH tHLQZ Q tHHQX tHHCH
D
HOLD
S tCH C tCLQV tCLQX Q tQLQH tQHQL D ADDR.LSB IN tCLQV tCLQX LSB OUT tCL tSHQZ
FIGURE 7-2: Expansion ROM Switching Characteristics.
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IP1000A LF
Preliminary Data Sheet
tcs
tcsh
EECS
tskl tcskv tskc tskh
IP1000A LF
EESK
tpd
EEDI
A7
A0 tdoh D15 D0
EEDO
tdos
FIGURE 7-3: EEPROM Switching Characteristics
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IP1000A LF
Preliminary Data Sheet
G M II T r a n s m it
T X D [7 ..0 ]
trv t rh
TXEN
trv t rh
TXER
trv t rh tcl tcc tch
G TXCLK
G M II R e c e iv e
IP1000A LF
R X D [7 ..0 ]
ts u
RXER
thd
ts u
thd
RXDV
ts u
RXCLK
thd
tcl
tcc
tch
G M II M a n a g e m e n t
M D IO
trv tsu thd tcl tcc tch
MDC
FI GURE 7-4: GMII Switching Characteristics
8
Order Information
Part No. IP1000A IP1000A LF Package 128-PIN LQFP 128-PIN LQFP Notice e-PAD package Lead free
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IP1000A LF
Preliminary Data Sheet
9
Package Detail
LQFP 128 Outline Dimensions
IC Plus Corp.
Headquarters 10F, No.47, Lane 2, Kwang-Fu Road, Sec. 2, Hsin-Chu City, Taiwan 300, R.O.C. TEL : 886-3-575-0275 FAX : 886-3-575-0475 Website: www.icplus.com.tw Sales Office 4F, No. 106, Hsin-Tai-Wu Road, Sec.1, Hsi-Chih, Taipei Hsien, Taiwan 221, R.O.C. TEL : 886-2-2696-1669 FAX : 886-2-2696-2220
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